Browsing by Subject "Spintronics"

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Characterization of Spin Hall and Magneto-ionic Devices for Logic, Memory and Neuromorphic Applications
(2021-07) Sahu, Protyush
This thesis is divided into two parts. In the first part, my research is focused on spin-to-charge conversion in amorphous Gd (40%)-alloyed Bismuth Selenide (60%) (BSG) thin films. The spin Hall effect has emerged as a key proponent for spintronic devices. Such devices typically consist of a bilayer structure made from a spin Hall channel and a ferromagnet. Polycrystalline Bi2Se3 was discovered to have a large spin Hall effect. Spin Hall angle and spin Hall efficiency (SCE) have been key parameters for comparing spin Hall channels. However, the output voltage becomes an essential requirement for spin logic devices, which also depends on resistivity. Gd (40%) alloyed Bi2Se3, grown by sputtering, can fill these gaps for spin logic devices. The material is amorphous, ensuring good scalability. Resistivity as a function of temperature showed strong signs of 3D variable range hopping with a characteristic Mott temperature of 9.7 x 105 K and a room temperature resistivity of 60,000 µOhm.cm. With 5nm in-plane CoFeB, the spin pumping results show good symmetric peaks for different excitation frequencies. The spin to charge conversion efficiency (~ Jc/Js) increased with decreasing thickness of BSG. Second harmonic measurements were performed to characterize thermal effects. The spin-orbit torque was negligible due to the dominance of thermal effects and current shunting through the ferromagnet. Anomalous Nernst effect was found to be the dominant thermal effect. However, it couldn’t explain our spin pumping results due to the lack of BSG thickness dependence and the dominance of the first harmonic voltage. The spin pumping was concluded to originate from the inverse spin Hall effect in BSG layer. My research focuses on irreversible magneto-ionic devices for one-time-programmable memory and neuromorphic applications in the second part of the thesis. Magneto-ionic devices rely on ionic movement through a gate dielectric to manipulate the magnetic properties of a magnetic material. We use Co20Fe60B20 perpendicular magnetic anisotropy (PMA) thin films. CoFeB/MgO interfacial PMA is a consequence of orbital overlapping between Oxygen and transition metal atoms. We further engineer the device to enable field-free magnetization switching. We use an exchange bias field from an adjacent ferromagnet ([Co(0.3nm)/Pd(0.7nm)]3) separated by a non-magnetic layer (Ta), forming a [Co(0.3nm)/Pd(0.7nm)]3/Ta/CoFeB/MgO structure. Pd (111) was used as the seed layer for [Co(0.3nm)/Pd(0.7nm)]3. The final stack is given by: Substrate/Ta(5nm)/Pd(10nm)/[Co(0.3nm)/Pd(0.7nm)]3/Ta(1nm)/CoFeB(1.3nm)/MgO(2nm). XRD and HRTEM were used to characterize the film, which showed distinct layers with some interdiffusion and a polycrystalline Pd(111). This stack is then topped with an ionic gate made from 100nm sputtered SiOx. AHE minor curves showed that the two ferromagnets have weak antiferromagnetic coupling. Application of negative gate voltage decreases the coercivity of CoFeB from ~34 Oe to 16 Oe, signaling a lowered PMA. The exchange bias field magnitude increases from ~ 25 Oe to ~ 45 Oe, due to the decrease in thickness of CoFeB. Major loop measurements show no change in [Co(0.3nm)/Pd(0.7nm)]3 layer with gate voltage. Oxygen ions from SiOx move towards the interface of MgO/CoFeB interface under negative gate voltage. This creates an overoxidation of the interface and destroys the interfacial PMA of CoFeB. This makes the CoFeB layer go from a bi-stable to a monostable state, resulting in a pathway for a field-free magnetization switch.
CMOS Reliability Characterization Techniques and Spintronics-Based Mixed-Signal Circuits
(2015-09) Choi, Won Ho
Plasma-Induced Damage (PID) has been an important reliability concern for equipment vendors and fabs in both traditional SiO2 based and advanced high-k dielectric based processes. Plasma etching and ashing are extensively used in a typical CMOS back-end process. During the plasma steps, the metal interconnect, commonly referred to as an “antenna,” collects plasma charges and if the junction of the driver is too small to quickly discharge the node voltage, extra traps are generated in the gate dielectric of the receiver thereby worsening device reliability mechanisms such as Bias Temperature Instability (BTI) and Time Dependent Dielectric Breakdown (TDDB). The foremost challenge to an effective PID mitigation strategy is in the collection of massive TDDB or NBTI data within a short test time. In this dissertation, we have developed two array-based on-chip monitoring circuits for characterizing latent PID including (1) an array-based PID-induced TDDB characterization circuit and (2) a PID-induced BTI characterization circuit using the 65nm CMOS process. As the research interest on analog circuit reliability is increasing recently, a few studies analyzed the impact of short-term Vth shift, not a permanent Vth shift, on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) and revealed that even short-term Vth shifts in the order of 1mV by short stress pulse (e.g., 1μs) on the comparator input transistors may cause to degrade the resolution of the SAR ADC even for a fresh chip (no experimentally verified). In this dissertation, we quantified this effect through test-chip studies and propose two simple circuit approaches that can be used to mitigate short-term Vth instability issues in SAR ADCs. The proposed techniques were implemented in 10-bit SAR ADC using the 65nm CMOS process. Spintronic circuits and systems have several unique properties including inherent non-volatility that can be uniquely exploited for achievable functional capabilities not obtainable in conventional systems. Magnetic Tunnel Junction (MTJ) technology has matured to the point where commercial spin transfer torque MRAM (STT-MRAM) chips are currently being developed. This work aims at leveraging and complimenting on-going development efforts in MTJ technology for non-memory mixed-signal applications. In this dissertation, we developed two spintronics-based mixed-signal circuit designs: (1) an MTJ-based True Random Number Generator (TRNG) and (2) an MTJ-based ADC. The proposed TRNG and ADC have the potential to achieve a compact area, simpler design, and reliable operation as compared to their CMOS counterparts.
Design and Optimization of Low-Power and High-Speed Spintronic Logic Devices
(2020-02) Mankalale, Meghna
Modern silicon transistor-based electronic circuits dissipate tremendous amounts of power as heat during computation. This has proven to be a bottleneck in making faster and smaller circuits. The sizes of the transistors on a chip have halved while their density on chip has doubled every 1.5 – 2 years for the last 50 years along a trajectory referred to as Moore's law. However, Moore's law is now losing steam due to the limitations of MOS transistors–mainly high power dissipation, limiting the further scaling of the MOS transistors. Thus, there is a need to search for replacement of the MOS technology to meet the increasing need for faster and more powerful electronics. The field of spintronics is often spoken as the most promising technology in this regard. Spintronics exploits this spin degree of freedom in electrons to perform computation. In spin-based devices, information is encoded in the collective spin or the net magnetization of a small magnet. Logic and memory operation is performed by manipulating the magnetization using physical phenomena. Spintronics promises (a) a very low energy computation to switch the magnetization between the two binary values, (b) nonvolatility and (c) novel functionalities. The design of spintronic devices poses a great challenge as it involves knowledge of complex physical phenomena, properties of materials, and a general understanding of devices and circuits to build large-scale systems. Several spin-based devices have been proposed recently. However, none of these focuses on building devices that are optimized for maximum performance, such as delay and energy dissipation. Therefore, large scale circuits using spin-based devices perform poorly when compared against the MOS technology. This thesis attempts to tackle this issue by (a) proposing optimization techniques to improve the energy and delay of the existing spin-based devices and facilitate easy design of large spin-based chips, and (b) propose new spin-based devices and novel circuit techniques that aims to exploit the spin-based physical phenomena that promises low-power operation. One of the most widely researched spin-based logic device candidates is called all– spin logic (ASL). In this thesis, we use a systematic approach to build an optimized ASL standard cell library. The ASL standard cells can then be easily used to build large spin-based circuits. First, we propose a novel technique to reduce the magnet count for implementing the AND gate using majority logic. We develop compact layouts for each logic gate in the cell library and use physics–based models to obtain the delay and energy of the logic gates. At the gate level, our method results in up to 24% faster and up to 47% more energy–efficient logic gates. At the circuit level, our method synthesizes ASL circuits that are up to 13% faster and up to 26% more energy–efficient compared to their corresponding unoptimized counterparts. We extend the base ASL scheme and propose a novel circuit level technique, called STEM (Scheme for Two-phase Evaluation of Majority Logic) that could be applied to any majority gate-based circuits to further reduce the power consumption. Such a two-phased technique results in an overall lower magnet count and a 1.6x–3.4x faster and 1.9x–6.4x more power-efficient ASL gates as compared to the traditional ASL implementation. To be competitive with MOS, spintronic logic devices should be both fast and dissipate low power. With this goal in mind, in this thesis, we explore two alternative devices. The first is CoMET (Composite Input Magneto Electric Logic Technology), a magnetoelectric (ME) effect-based device, which has the potential for very low power device operation. We use physics–based models for the ME effect and domain walls to obtain the performance metrics of CoMET. We build a compact CoMET device and perform optimizations at (a) the device level over different material parameter combinations, and (b) the circuit–level for easy cascading of devices to obtain a 27× faster device at similar energy compared to existing ME devices. CoMET significantly outperforms MOS technology for energy-harvesting applications, by exploiting its nonvolatility. The second proposed device is based on skyrmions, which are magnetic vortex- like nanostructures that have shown promise due to their robustness to pinning in the magnetic films and their potential to be miniaturized to a diameter of a few nanometers. In this thesis, we present a skyrmion-based device, SkyLogic, and create a framework for analyzing its performance. We also propose a novel circuit technique to counter the transverse motion of the skyrmion along with its longitudinal motion which significantly increases the skyrmion propagation latencies, thereby incurring large device delay. We optimize the performance of the device over different material combinations to obtain an optimal design point. The last part of the thesis addresses the design of non-Boolean neuromorphic systems based on emerging spintronic devices. Advances in artificial intelligent systems have been primarily driven by the widespread adoption of neural networks. We explore the use of spiking neural networks (SNNs) that use information spikes to transmit information, much like the human brain. CMOS-based hardware to implement SNNs are not power efficient because of the data-intensive nature of the SNNs. We build a compact neuron hardware substrate for SNNs, which form the fundamental building block of a neural network. We then implement an all ferroelectric FET (FeFET)-based unsupervised winner-takes-all SNN and show how this platform can be used to perform handwritten digit recognition on the MNIST database. The procedure use FeFET models to tune the neuron behavior to increase the accuracy of the SNN. We show that our implementation results in a very high accuracy for a compact implementation of the FeFET-based SNN.
Design, Simulation, and Optimization of Spintronic Logic Devices
(2019-02) Liang, Zhaoxin
Over the past 50 years, complementary metal-oxide-semiconductor (CMOS) technology has developed aggressively and has undergone continuous scaling, as described by to Moore's Law. However, as transistor feature sizes approach the nanometer scale, there have been growing concerns with escalated power dissipation issues in very large scale integrated (VLSI) circuits, as well as device performance/reliability issues under process variations and aging. Meanwhile, emerging consumer electronic markets such as mobile and distributed computing, the internet of things, and autonomous driving platforms have posed various new challenges for the reliability and performance of electronic systems. While mainstream efforts have pushed forward scaling in CMOS technologies, there has been growing research interest in search for replacements for CMOS. Such efforts involve conceptualizing computational devices, based on new physics principles and new materials, that could serve as fundamental building blocks for new architectures, providing diversified computational functionality and offering better performance than the traditional CMOS-based paradigm. Among these beyond-CMOS technologies, spintronics is one of the most promising candidates for building next-generation logic devices. Spintronics takes advantage of an intrinsic property of electrons, spin, and develops the concept of state based on magnetism, which is a physical manifestation of electron spin. However, this new technology requires new simulation frameworks and design methods to be developed and deployed in order to propose and evaluate the potential of new spin-based devices, accounting for the impact of novel material properties that dictate the performance of these devices. Such frameworks can further be employed in determining the dependence of circuit performance on material and device parameters, and in optimizing these new technologies. The first part of the thesis provides a brief review of spintronics and explains a set of physical effects that are exploited to build spintronics-based devices descried in the later chapters. These include spin transfer torque (STT), which forms the basis for early spin-based logic devices, with its associated concepts of spin polarized current and non-local spin valve structure; the magnetoelectric (ME) coupling effect that provides low power and fast switching of magnetization in a ferromagnet (FM) with multiferroic material stacks; domain wall (DW) structures in FMs that can be used for logic transfer; and inverse spin orbit coupling (ISOC) effects, which offer convenient conversion between spin and charge states. The second part of the thesis develops performance optimization techniques for all-spin logic (ASL) devices. A framework for simulating ASL devices is first described, and a method for performance optimization through device sizing is developed. An algorithm for optimal device sizing, based on the geometrical dependence of the energy and delay for the ASL device, is then developed. The results of optimization on standard circuit benchmarks, implemented with ASL gates, are shown and the energy/delay trade-off relation is explored. The third part of the thesis introduces a new device, composite oxide magnetoelectric logic technology (CoMET), and the role played by this thesis research in developing the device. CoMET employs DW as the logic transfer medium and uses the ME coupling effect as well as its inverse effect to realize fast DW creation and detection. A composite structure with magnetization coupling existing between in-plane FM and perpendicular FM is added to the input end of the device in order to further lower the energy of the nucleation process. A detailed study of how this device nucleates a DW at the input end is conducted, and it is demonstrated how input nucleation can be performed in a fast and power-efficient way, leading to a high-speed, low-power CoMET device implementation. The pinning effect with random artificial defects of various sizes is discussed to show how such defects mitigate DW oscillation after nucleation. Such oscillations are seen in idealized defect-free DW structures that are typically simulated by researchers using micromagnetic simulators. The final part of the thesis studies the magnetoelectric spin orbit coupling (MESO) device that was recently proposed by researchers at Intel. The thesis presents a simulation framework and evaluates the performance of the device through detailed modeling, analysis and simulation. It is shown that when devices are cascaded, potential sneak path could corrupt the computation, and solutions to avoid this problem are proposed. To extend MESO to build general logic, two majority gate designs, based on a DW majority and a charge-based majority, are demonstrated and evaluated. It is shown under some scenarios, the charge-based majority gate may not provide correct output values and must be carefully designed to avoid these scenarios.
Development of next generation computing elements fabricated with emerging technologies.
(2011-12) Patil, Shruti
Revolutionary developments in the electronics industry have enabled rapid and unprecedented advances in modern systems. This has been achieved in part due to an aggressive push towards technological developments by the semiconductor industry. The electronics technology has sustained this steep trend, however, the International Technology Roadmap for Semiconductors (ITRS) that assesses future technology requirements, has identified several fundamental challenges of scalability, speed, energy and reliability that can severely limit the ability of CMOS devices to continue to maintain the sharp developmental curve. These challenges, and the discovery of new physics effects and materials, have ushered in several efforts dedicated to researching new technologies that can help support the aggressive technological roadmap. The emerging technologies bring novel capabilities for computing, however, there are large gaps in our understanding of these new technologies and how to build circuits with them, that must be filled before they can be integrated into computing systems. This thesis focuses on evaluating the computing potential of two promising, emerging technologies: Nanoelectromechanical systems (NEMS) and Spintronics. Both technologies differ in their device physics and capabilities from electronic MOSFET devices, and pose novel challenges for integration into current computing systems. The devices from the NEMS technology are extremely power-effcient, however they have a high mechanical delay. To allow the NEMS devices to serve as effective digital switches, a novel logic design technique called `weighted area logic' that addresses the fundamental delay challenge of the devices has been proposed. The new design technique also reduces power and area of implementation by reducing the number of devices in a circuit. Devices from the Spintronics technology are based on magnetic effects and do not directly replace the switch-based electronic transistors. Their singular characteristics necessitate novel ideas to enable logic operations. Some of the differences of the devices from CMOS devices affect fundamental abilities that computing circuits are generally founded on. These include input-output signal compatibility, scalability of logic circuits and composability. Circuit designs and techniques that address these three challenges are proposed and studied using the spintronic devices of Magnetic Tunnel Junctions (MTJs). A novel MTJ-based logic circuit that operates completely on spintronic principles and has spintronic input-output compatibility is designed and evaluated. An extension of this circuit into a scalable and programmable logic circuit is also proposed. The idea of combining the unique device capability of processing and storage is also presented through the design of a Spintronic Logic In Cache unit. Further, the design for an 8-function 1-bit spintronic arithmetic and logic unit has been proposed.
Dynamics and performance optimization of spin-torque switching in magnetic tunnel junctions
(2013-10) Dunn, Thomas Edward
In this thesis I present a theoretical description for spin-torque switching using AC and DC spin-currents. This description builds from the standard Landau-Lifshitz-Gilbert equation with Slonczewski spin-torque. By exploiting a separation in time-scales between the fast precessional motion of the free layer magnetization about the effective field and the slow drift of the free layer towards higher or lower energies that results from ST and damping, I reduce the free layer switching dynamics to that of a one dimensional system. Using this description I characterize certain current and frequency values important to switching, such as the DC critical current and the AC upper bifurcation frequency. Finally, using this description I show how to optimize the efficiency of AC, DC, and combination AC/DC spin-current strategies to minimize the Joule heat loss associated with switching. This leads to a well-defined range of spin-current polarization and free layer anisotropy values where each spin-current strategy is optimal.
Efficient and Reliable In-Memory Computing Systems Using Emerging Technologies: From Device to Algorithm
(2021-11) Zabihi, Masoud
Big data applications are memory-intensive, and the cost of bringing data from the memory to the processor involves large overheads in energy and processing time. This has driven the push towards specialized accelerator units that can perform computations close to where the data is stored. Two approaches have been proposed in the past: (1) near-memory computing places computational units at the periphery of memory for fast data access, and (2) true in-memory computing uses the memory array to perform computations through simple reconfigurations. Although there has been a great deal of recent interest in the area of in-memory computing, most solutions that are purported to fall into this class are really near-memory processors that perform computation near the edge of memory arrays/subarrays rather than inside it. This thesis discusses several years of effort in developing various true in-memory computation platforms. These computational paradigms are designed using different emerging non-volatile memory technologies such as spin transfer torque (STT) magnetic tunnel junction (MTJ), spin Hall effect (SHE) MTJ, and phase change memory (PCM) device. The proposed platforms in this thesis effectively eliminate the energy and delay overhead associated with data communication. Our approach is digital, unlike prior analog-like in-memory/near-memory solutions, which provides more robustness to process variations, particularly in immature technologies than analog schemes. The thesis covers alternatives at the technology level, followed by a description of how the in-memory computing array is designed, using the basic non-volatile unit (such as MTJ) and some switches, to function both as a memory and a computational unit. This array is then used to build gates and arithmetic units by appropriately interconnecting memory cells, allowing high degrees of parallelism. Next, we show how complex arithmetic operations can be performed through appropriate scheduling (for adders, multipliers, dot products) and data placement of the operands. We demonstrate how this approach can be used to implement sample applications, such as neuromorphic inference engine and a 2D convolution, presenting results that benchmark the performance of these CRAMs against near-memory computation platforms. The performance gains can be attributed to (a) highly efficient local processing within the memory, and (b) high levels of parallelism in rows of the memory. For our in-memory computing platforms, wire resistances and variations are a substantial source of non-ideality that must be taken into account during the implementations. To ensure the electric correctness of implementations, we have developed different frameworks to analyze the parasitic effects of wires based on actual layout considerations. We have demonstrated that interconnect parasitics have a significant effect on the performance of the in-memory computing system and have developed a comprehensive model for analyzing this impact. Using this methodology, we have developed guidelines for the physical parameters such as array size and numbers of rows and columns.
Electron spin-flip scattering in graphene due to substrate impurities
(2013-01) Goswami, Aditi
Graphene has long been known for its peculiar Dirac-like band structure which lends it many of its remarkable properties. It is a promising material for electronic and spintronic applications due to its high carrier mobility, low intrinsic spin-orbit interaction and small hyperfine coupling. However, extrinsic effects may easily dominate intrinsic mechanisms. The scattering mechanisms investigated here are those associated with non-magnetic, charged impurities in the substrate (e.g. SiO2) beneath a planar n-type graphene layer. Such impurities cause an electric field that extends through the graphene and has a non-vanishing perpendicular component. Consequently, the impurity, in addition to the conventional spin-conserving scattering can give rise to spin-flip processes. The latter are a consequence of a spatially varying Rashba spin-orbit interaction caused by the electric field of the impurity in the substrate. This work focuses on the calculation of the elastic scattering cross-sections for these mechanisms. Additionally, relaxation times are estimated for assumed impurity concentrations.
Exploring a multiprocessor design space to analyze the impact of using STT-RAM in the memory hierarchy
(2014-09) Borse, Nishant Ashok
Spin-tronic memory is a promising technology and offers advantages due to its non-volatility and higher density. At the same time, based on device properties, there are trade-offs that decide the energy and performance penalty overhead. To decide these trade-offs its it imperative to understand the sensitivity of different parameters in the memory subsystem. In this work, we use a known statistical technique to analyze processor core and memory parameters for their sensitivity towards performance and energy for a Spin-tronic based memory hierarchy. We also study how does the sensitivity of processor core parameters like Re-order buffer, Load Store queue etc. vary when we replace a traditional SRAM memory with the new spin-tronic technology. Further, given a mix of different memory technologies and important processor core parameters, we use find the optimal configuration for delay, energy and area using the method of simulated annealing.
Generation and Absorption of Pure Spin Currents Using Graphene Nonlocal Spin Valves
(2018-01) Stecklein, Gordon
This work describes the fabrication and measurement of nanoscale devices in which a spin-polarized electrical current is used to inject spins into graphene, which then diffuse. We demonstrate the electrical detection of spins in graphene devices with micron-scale spin diffusion lengths and analyze how the spin lifetime and spin diffusion lengths are affected by electrostatic gating. The spin current absorbed by an adjacent ferromagnet is calculated and demonstrated to increase as the electrical conductance of the graphene/ferromagnet interface is improved. Quantitative modeling, including a finite element model of the spatial distribution of spins and the effect of a thin metallic island, indicates that the absorbed spin current is nearing the regime necessary for future technological applications.
Generation of Spin Currents for Spintronic Logic Applications
(2016-04) Smith, Angeline
Current complementary metal oxide semiconductor (CMOS) technologies currently suffer drawbacks such as increased power consumption and device variability with scaling as well as volatility. In order to further advance computation technologies in the future, new and alternative devices are being explored to overcome these limitations. One promising approach is spintronic devices in which information is stored and computed based on the spin of electrons rather than the absence or presence of charge such as in CMOS. Spintronics offers many possible benefits including fast operational speed, low power consumption, and nonvolatility. This dissertation explores methods of generating spin polarized currents for the operation of logic devices and the fabrication of these devices for logic applications. The first device explored is a non-local lateral spin valve which can be used to generate a pure spin current and is the basic building block for the concept of all-spin logic. A unique top-down fabrication approach for lateral spin valves is created and demonstrated. Sub 100nm Co nanopillar devices are fabricated on a Cu channel using a top down approach that allows the entire material stack to be deposited initially under vacuum as opposed to devices fabricated using shadow beam lithography or lift-off techniques for ferromagnetic strips. A non-local signal is measured in these devices which indicates the top-down approach can successfully be used for integration of these devices. This demonstration is essential for these devices to be successfully implemented and scaled in computer applications at the industrial level. . In the second part of the dissertation, my research on spin Hall effect devices and the application of these devices for a spin Hall majority gate logic device are presented. The spin Hall effect is explored in bulk perpendicular TbFeCo/Ta devices which lays the groundwork for the following experiments. Then, a composite spin Hall structure is developed in order to switch perpendicular magnetization using the spin Hall effect without the need for an externally applied field. To demonstrate the ability to tune the material properties of a spin Hall channel, studies are also presented on a variety of multilayer spin Hall devices. Last, a three-input MTJ device is proposed for a spin orbit torque combined with spin transfer torque majority gate. Three MTJ devices are fabricated on Ta and three distinct switching states are shown corresponding to switching of the individual input elements. Additionally, simulation work is presented to verify the concept of the majority gate.
Graphene Lateral Spin Valves For Computing And Magnetic Field Sensing Applications
(2019-01) Hu, Jiaxi
The current complementary metal–oxide–semiconductor (CMOS) technologies are facing greater-than-ever challenges as the Moore’s law approaches to its physical limits. The search for future electronic devices began decades ago. Spintronics, which utilizes the properties of electron spins, is indeed one of the most promising solutions for the beyond-CMOS era. Over the past years, spintronics has been very successful in Hard-disc drives (HDDs) and has significantly increased the storage areal-density. Recently, because of its built-in non-volatility, spintronics has also demonstrated its potential in memory applications. On the other hand, graphene, which is a monolayer of carbon atoms arranged in hexagonal order, is very attractive as the material for spin transport. For example, graphene has the longest spin diffusion length and spin lifetime at room temperature. Therefore, as the device that combines the unique properties from both sides, the graphene lateral spin valve can be useful in many applications. This dissertation mainly explores the use of graphene lateral spin valves for future computing and magnetic field sensing applications. This thesis firstly discusses the spin-circuit model, which is capable of simulating the dc, ac and transient behavior spintronic devices. Using the spin-circuit model, the scaling and energy consumption of all-spin logic devices is quantitatively studied. As one of the original proposals for spin-based computing, ASL utilizes lateral spin valves to process information in the spin domain. By using the physics-based spin-circuit model, the simulations suggest the effect of output-input isolation may be the fundamental challenges that prevent ASL from competing with CMOS in the scheme of conventional Boolean-computing. Next, this thesis explores the application of graphene lateral spin valves in non-Boolean computing and presents an implementation of spintronic Cellular Neural Networks (CNNs). In the graphene-based spintronic CNNs, weights are programmed as spin currents. Because of the tunable spin diffusion length in graphene, the weights can be controlled as local gate voltages, which can tune the weight values over a wide range. The simulation results show that the graphene-based spintronic CNNs have significantly improved scalability, particularly as the number and accuracy of synapses increases. In the last part of this thesis, the width scaling of graphene spin channels is experimentally studied, which is crucial for both the computing and magnetic field sensing applications. By using the graphene deposited by chemical vapor deposition (CVD) and a dedicated fabrication process, a large number of graphene lateral spin valves with consistent interface properties but different channel aspect ratios are fabricated on a single chip. The experimental results show that, as the channel width is scaled from 10 µm to 0.5 µm, the change in the nonlocal spin resistance matches the theory of contact-induced spin relaxation with the interface spin polarization, P, of 3 – 5 %, and spin diffusion length, λs, of 1.5 – 2.5 µm. Meanwhile, the spin-independent baseline resistance dramatically decreases due to the reduction in charge current spreading. However, we find that a remnant baseline remains due to the thermoelectric effects of graphene. By using the gate-voltage and bias-dependent analyses, we attribute the remnant baseline signal to the Joule-heating induced Seebeck voltage. These results suggest that in lateral spin valve design, to avoid any background signals, both the charge and thermal equilibrium conditions should be satisfied.
High Anisotropy Magnetic Materials for Data Storage and Spintronic Memory
(2018-01) Quarterman, Patrick
Data storage technologies that utilize magnetic materials for storage are key for both increasing areal density of storage in traditional hard disk media and providing low energy alternatives to traditional CMOS technology through spintronic memory and logic devices. Spintronic memory relies on the spin of an electron rather than charge and is a promising candidate for achieving non-volatility which can provide dramatic energy savings. A key challenge for magnetic based storage is achieving 10 nm or smaller feature sizes while retaining thermal stability. This requires development of magnetic thin films with large magnetocrystalline anisotropy. Switching the magnetization of high anisotropy magnetic materials requires large Oersted field or spin current. One way to decrease the switching energy is to lower the anisotropy during the switching process with an applied strain or heat. This scheme retains thermal stability during storage and makes write energies feasible from a technological aspect. Development of suitable high anisotropy materials at sub 10 nm scale has proved difficult due to limitations on traditional thin film growth methods, nanoscale effects, and additional requirements on materials for memory applications. The effect of a static strain on the magnetic anisotropy is well understood, but less so for application in devices which require fast switching and high cycling. The other approach to lowering switching energies is to use magnetic materials with small magnetization, such as Mn-based compounds. I will discuss my experiments to advance understanding of: development of FePt for HAMR media, effect of strain assisted switching on the spin state of FePt, and development of novel high anisotropy Mn-based materials with low magnetization. Finally, I will present my experimental realization of Ru as the 4th room temperature ferromagnetic element. Ru has been predicted to become ferromagnetic when placed into a metastable tetragonal or cubic phase. This new phase of Ru also has potential to achieve the requirements for a viable spintronic device. I will show my work on the realization of the tetragonal phase Ru using seed layer engineering in thin films, and its associated ferromagnetic properties.
High Charge-to-Spin and Spin-to-Charge Conversion Enhanced by Quantum Confinement Effect in Sputtered Topological Insulator Thin Films
(2019-01) DC, Mahendra
The spin-orbit torque (SOT) arising from materials with large spin-orbit coupling promises a path for ultra-low power and fast magnetic-based storage and computational devices. The SOT switching of magnetization can be used in the SOT-memory and computational devices whereas the spin-to-charge conversion can be utilized for reading of magnetization state in computational devices. Recent reports on topological insulators show high SOT but the industry compatible growth process is still lacking. Furthermore, SOT switching of perpendicular magnetization from topological insulators is demonstrated but still with large current density and large external field. We investigated the SOT from magnetron-sputtered bismuth selenide thin films in BixSe(1-x)/Co20Fe60B20 heterostructures by using dc planar Hall and spin-torque ferromagnetic resonance (ST-FMR) methods. Remarkably, the spin torque efficiency ( ) was determined to be as large as 18.62 ± 0.13 and 8.67 ± 1.08, using the dc planar Hall and ST-FMR methods, respectively. Moreover, switching of perpendicular CoFeB multilayers using SOT from the BixSe(1-x) has been observed at room temperature (RT) with low critical magnetization switching current density ( ) 4.3 × 105 A/cm2. Quantum transport simulations using realistic sp3 tight binding model suggests that the high SOT in sputtered BixSe(1-x) is due to a quantum confinement effect, whose charge-to-spin conversion efficiency enhances with reduced size and dimensionality. The demonstrated , ease of growth of the films on a silicon substrate, and successful growth and switching of perpendicular CoFeB multilayers on BixSe(1-x) film provide an avenue for the use of bismuth selenide thin films as a spin-density generator in SOT-based memory and logic devices. In addition to charge-to-spin conversion, we also performed spin-to-charge conversion by sputtered bismuth selenide thin films. For the spin-to-charge conversion experiment, we prepared Sub/Si/SiO2/Bi43Se57/Co20Fe60B20 heterostructures with in-plane magnetization. High spin-to-charge conversion voltage signals have been observed at room temperature. The spin-pumping voltage decreases with an increase in the size of the grains. The figure-of-merit of spin-to-charge conversion inverse Edelstein effect length ( ) is estimated to be as large as 0.32 nm. The large is due to the spin-momentum locking and is further enhanced by quantum confinement in the nano sized grains of the sputtered bismuth selenide films. We also investigated the effect on spin-pumping voltage due to the insertion of layers MgO and Ag. The MgO insertion layer has almost completely suppressed the spin-pumping voltage whereas Ag insertion layer has enhanced the spin-pumping voltage as large as 40%. The suppression of spin-pumping voltage due to the insertion of insulating layer indicates that the thermal effects are negligible in the spin-pumping signal. The enhancement of spin-to-charge conversion voltage by insertion Ag layer is due to the Rashba-Edelstein effect. Moreover, the conducting ferromagnetic layer can influence both SOT and spin-to-charge conversion voltage. We investigated spin-to-charge conversion in sputtered Y3Fe5O12(YIG)/BS bi-layers at room temperature. The spin current is pumped to the BS layer by the precession of magnetization at ferromagnetic resonance in the YIG layer. is estimated to be as large as (0.11 ± 0.03) nm in YIG/BS (4 nm). Moreover, also shows a dependence on the bismuth selenide film thickness in YIG/BS structure, which is consistent with the spin-to-charge conversion in conducting ferromagnet and also in case of charge-to-spin conversion.
Hyperfine effects in ferromagnet-semiconductor heterostructure
(2010-04) Chan, Mun Keat
This thesis describes the effect of hyperfine interactions on non-equilibrium electron spins in Fe/GaAs heterostructures. Nuclei in bulk GaAs are dynamically polarized by a non-equilibrium electron spin population injected through an Fe/GaAs Schottky tunnel barrier. The polarized nuclei in turn exert a large hyperfine field upon the electron spins, resulting in rapid electron spin precession. Electrical measurements of the steady state electron spin polarization as a function of applied magnetic field for various injector biases and temperatures allow us to extract the electron spin lifetime, Knight shift, and nuclear field parameters in bulk GaAs. We successfully model electron spin dynamics using a coupled electron-nuclear drift diffusion equation. We confirmed the strong hyperfine coupling between electron and nuclear spins by performing nuclear magnetic resonance measurements on Fe/GaAs devices in applied fields of only a few hundred Oe. Resonant frequencies of different isotopes in the GaAs channel were detected. In addition to exerting a hyperfine field on the electron spins, we also observe a hyperfine induced spin-dependent Hall effect measured across the spin-polarized region of a GaAs channel. Application of a transverse magnetic field results in a modulation of the Hall voltage consistent with spin de-phasing. This signal changes sign when the magnetization of the Fe contact is switched, indicating sensitivity to electron spin direction. The observed spin-dependent Hall signal is approximately two orders of magnitude larger than that expected from previous measurements of the spin Hall effect in n-GaAs, which was attributed to spinorbit coupling and impurity scattering. This suggests that a different mechanism is active in our system. We demonstrate full suppression of the spin-dependent Hall signal by eliminating nuclear polarization through a field cycling procedure. Additionally, while the electron spin accumulation, detected by a spin sensitive Fe contact, persists up to 200 K, the spin-dependent Hall signal is not observed above 120 K, in coincidence with the disappearance of the nuclear spin polarization due to delocalization of donor electrons. We conclude that the observed spindependent Hall signal is coupled to the nuclear spin polarization. This is the first observation of a hyperfine-induced spin Hall effect.
Iron Nitride Based Magnetoresistance Devices For Spintronic Applications
(2018-03) Li, Xuan
The iron nitrides have been attracting a wide interest in spintronics researches due to their unique magnetic properties. In this thesis, I describe the experimental studies of the spintronic devices based on two important iron nitride materials, i.e. Fe16N2 and Fe4N. In the Fe16N2 based magnetoresistance device development, a heavy-metal free, low damping, and non-interface perpendicular current-perpendicular-to-plane (CPP) giant magnetoresistance (GMR) device with Fe16N2 magnetic layers has been demonstrated. The crystalline based perpendicular anisotropy of the Fe16N2 in the CPP GMR device is measured to be about 1.9 e7 erg/cm3, which is sufficient to maintain the thermal stability of the sub-10nm devices. The damping constant of the Fe16N2 thin film is determined to be 0.01 by a ferromagnetic resonance measurement, which is much lower than most existing materials with crystalline perpendicular magnetic anisotropy. The non-interface perpendicular anisotropy and low damping properties of make Fe16N2 a promising material for future spintronic applications. In the Fe4N material and device studies, both the (111) oriented and (001) oriented Fe4N thin films are prepared by optimizing the buffer layers, substrate temperatures and N:Fe composition. The most attractive properties of Fe4N in spintronics are the large spin asymmetric conductance and the negative spin polarization. The spin polarization of the (111) oriented Fe4N is investigated. The thickness dependence of the spin polarization of the (111) oriented Fe4N is also explored. Moreover, I have studied the Gilbert damping constant of the Fe4N (001) thin film by ferromagnetic resonance. The αFe4N is determined to be 0.021±0.02. Last but not least, the current-perpendicular-to-plane (CPP) giant magnetoresistance (GMR) device with Fe4N/Ag/Fe sandwich have also been fabricated and characterized. Giant inverse magnetoresistance is observed in the Fe4N based CPP GMR device, which confirms that the spin polarization of Fe4N and Fe4N/Ag interface is negative.
Magnetic Tunnel Junctions For Next Generation Of Conventional And Unconventional Computing Schemes
(2022-09) Zink, Brandon
Magnetic tunnel junctions (MTJs) have several novel features that make them promising devices for next generation memory and computing technologies. These features include multifunctionality, tunable stochasticity, and capability of being tuned by multiple forces. In this dissertation, I demonstrate how these properties make MTJs promising solutions in conventional memory and logic applications as well as unconventional computing applications such as probabilistic bits with increased information capacity and stochastic computing units. Devices that generate random asynchronous, or telegraphic, switching signals have been proposed as probabilistic bits (p-bits) in new paradigms of probabilistic computing schemes for advanced computation. For the first part of my dissertation, I demonstrate that tunable telegraphic switching signals can be generated from MTJs through the combination of an external magnetic field and a DC bias voltage. Previous studies show that tunable telegraphic signals can be generated on MTJs with low thermal stability using only a single bias current or bias voltage. However, my results show that this ‘dual-biasing’ method has a unique capability called two-degrees of tunability, which gives this method two key advantages over the single biased method. One is that it can overcome the challenges imposed by the effects of device variations in large-scale networks and the second is that the signals generated have two times more information capacity than those generated by single-biased MTJs. In the next part of my dissertation, I explore the interplay between the effects of the voltage-controlled exchange coupling (VCEC) and spin-orbit torque (SOT) switching mechanisms. Previous experimental work from our group has demonstrated that VCEC switching can be achieved in perpendicularly magnetized MTJs (p-MTJs) at switching current densities nearly one order of magnitude lower than those for spin transfer torque (STT) and SOT switching. In this dissertation, I show that by combining the SOT and VCEC effects, the VCEC switching current density can be reduced even further, thus providing a pathway to optimize the performance of future magnetoresistive random access memory (MRAM) technologies based on VCEC switching. In the next chapter, I describe a method that was invented by our research group that performs stochastic computing within the hardware for computational random-access memory (CRAM), which is called SC-CRAM. Stochastic computing has several attractive capabilities such as performing complex arithmetic functions with a small number of logic gates, noise resilience, and error tolerance. However, there are significant costs in circuit area and energy consumption for the hardware required to generate stochastic bit-streams. The method described in my dissertation overcomes these costs by embedding the bit-stream generation and computation steps within the same CRAM cells. Furthermore, SC-CRAM shows significant reductions in circuit area for certain neuromorphic computing tasks when compared to conventional computing methods in CRAM. Finally, I study the prospects of MTJs for future applications involving high radiation environments, such as space exploration. Ionizing radiation levels beyond 10 krad have detrimental effects on modern CMOS technology. However, my results demonstrate that MTJs can be exposed to ionizing radiation levels as high as 1 Mrad without significantly influencing the properties key to their performance in MRAM cells. This resilience to ionizing radiation makes MTJs strong candidates for future ‘rad-hard’ devices.
Materials Research for High Efficiency Spin Orbit Torque Plus Voltage Controlled Magnetic Anisotropy Magnetoresistive Random-Access Memory
(2022-05) peterson, thomas
Current magnetoresistive random-access memory (MRAM) products utilize spin-transfer torque (STT) writing which requires large critical current densities, limiting the device lifetime as these large currents are forced through the tunneling barrier. Spin-orbit torque (SOT)-MRAM is a promising alternative to STT that circumvents many of STT’s issues by generating spin currents in a spin orbit torque channel under the free layer without interacting with the tunneling barrier. Decreasing the power consumption of SOT-MRAM requires materials with large spin torque efficiencies and low resistivities, such as heavy metals and topological semi-metals. A further decrease in power consumption can be realized by utilizing the voltage controlled magnetic anisotropy (VCMA) effect, which allows for a dynamic reduction in magnetic anisotropy with an applied voltage, lowering the switching energy while retaining high anisotropy for thermal stability. However, typical MTJ material stacks have shown minimal linear VCMA responses. Recent theoretical works have predicted a large and bidirectional VCMA effect at high levels of electron depletion, however, the required voltages to achieve these levels of depletion are beyond the dielectric breakdown of experimental gates. Inserting high work-function materials underneath the magnetic layer will deplete electrons from the magnetic layer, creating a built-in bias voltage. This can shift the gating window into the electron-depleted regime where the pJ/Vm and bidirectional VCMA effect was predicted.
Micromagnetic Modeling of Magnetic Storage Devices
(2021-03) Hsu, Wei-Heng
Hard disk drives (HDDs) are the dominant mass storage devices for personal and cloud storage due to their low cost and high capacity. Heat-assisted magnetic recording (HAMR) is considered to be next-generation recording technology for HDDs. While HAMR shows the potential for areal density to go beyond one terabit per square inch, this new recording mechanism requires further understanding and optimization before commercialization. First, I examine the relationship between media noise power and linear density in HAMR. I observe that there is a noise plateau at intermediate recording density and show that the plateau can be shifted to different recording density regions depending on the temperature profile. This effect is argued to be a consequence of the competition between transition noise and remanence noise in HAMR. To extend the recording density limit, heat-assisted shingled magnetic recording is studied. The transitions are no longer symmetric about the track center after shingled writing, especially when the transitions are highly curved as a result of the temperature profile generated by the near-field transducer. I propose a new reading scheme by rotating the read head to match the curved transitions. For a single rotated head, more than 10% improvement in user density over that of a single non-rotated head is achieved. I found that the optimal rotation angle generally follows the transition shape. With an array of two rotated heads, a track pitch of 15 nm, and a minimum bit length of 6.0 nm, the user areal density reaches 6.2 terabits per square inch, more than 30% above previous projections for recording on granular media. Magnetoresistive random-access memory (MRAM) is another type of magnetic storage device that is mainly used as computer memory. As semiconductor-based memory begins to hit physical limits, spin-transfer torque (STT) MRAM and spin-orbit torque (SOT) MRAM appear to be strong candidates for future memory applications. I start first by studying SOT switching in magnetic insulators. Magnetic insulators (MIs), in particular rare-earth iron garnets, have low damping compared to metallic ferromagnetic materials due to lack of conduction electrons. Analogous to STT devices, their low-damping nature is presumed to be an advantage for SOT applications. I report that perpendicular magnetic anisotropy (PMA) material with low damping does not favor reliable SOT switching, but increased damping, interfacial Dzyaloshinskii–Moriya interactions, or field-like torques may help SOT switching in some cases. Notches in a nanometer-scale element, which is a more realistic size for practical applications, can also improve switching stability. To fully utilize low damping MIs with SOT, an in-plane exchange-coupled composite free layer SOT-MRAM is proposed. The free layer consists a low-damping soft MI and a high anisotropy material. The adoption of high anisotropy materials, such as L10 alloy, not only facilitates the achievement of ultra-high-density memory but also allows for the reduction of heavy metal layer volume and thus a reduction in write energy not seen in previous CoFeB-based SOT-MRAM. A write energy of 18 attojoules per bit for 1 ns switching is achieved which is only 72 times more than the theoretical limit of 60kBT. It also represents a factor of more than five hundred times improvement relative to state-of-the-art dynamic RAM.
Non-volatile In-memory Computing for Large Scale Data-Intensive Workloads: Challenges and Opportunities
(2021-12) Chowdhury, Zamshed
The application(domain)s that depend on the large amount of data for solving problems, e.g., genome sequence analysis, graph analytics, machine learning etc., suffer from growing overhead of data communication between physically separate logic (i.e., compute) and memory elements in conventional von Neumann computing. The recent progress in processing(/computing)-in-memory (PIM/CIM) or simply, in-memory computing addresses data communication overhead in these applications by fusing compute capability with memory where the data reside– thereby achieving reduced energy consumption, and higher application throughput due to access to the higher internal bandwidth of the memory substrate as compared to the off-chip bandwidth.In this thesis, we focus on the architecture- and application-level characterizations of PIM architecture, Computational RAM (CRAM) in particular, for large scale data-intensive workloads–in terms of opportunities and challenges. We demonstrate the efficacy of CRAM in reducing the communication bottleneck of genomic sequence analysis, as a representative application domain due to its importance and inherent characteristics that are suitable for PIM-based implementation, by designing various CRAM-based Hardware (HW) accelerators. The designs cover all architectural aspects such as data layout, spatio-temporal scheduling of compute, system integration etc. First, we introduce an in-memory accelerator architecture, BWA-CRAM, for DNA sequence alignment by direct mapping of state-of-the-art Burrows–Wheeler Aligner algorithm on CRAM. This architecture outperforms corresponding software implementation in terms of throughput and energy efficiency, even under conservative assumptions. Next, we improve the performance of DNA sequence (pre-)alignment (and other similar, generic pattern matching applications) through HW/SW co-design and introduce SpinPM, a novel high-density, reconfigurable spintronic in-memory pattern matching substrate based on CRAM with Spin-Orbit-Torque (SOT)– specifically Spin-Hall-Effect (SHE) MTJ devices; and demonstrate the performance benefit SpinPM can achieve over conventional and near-memory processing systems. Subsequently, we present CRAM-Seq, an accelerator for RNA-Seq abundance quantification based on CRAM. Through HW/SW co-design, we demonstrate that CRAM-Seq outperforms a commonly used state-of-the-art software abundance quantification algorithm, Kallisto, in terms of throughput and energy efficiency. We introduce Content Addressable Memory or CAM, which is very efficient in large scale pattern matching, functionality in CRAM, next. We present CAMeleon- a novel compute substrate that leverages the high energy efficiency benefit of CRAM, and is capable of satisfying very stringent hardware resource (area) budget in embedded/edge computing applications, e.g., handheld sequencing device. CAMeleon performs CAM operations more energy-efficiently while consuming less/similar area, and supports logic and memory functions beyond CAM operations on demand through reconfiguration, as compared to conventional CAM-only designs based on SRAM and emerging memory technologies (such as STT-MTJ, ReRAM and PCM). Finally, we study the impact on applications’ reliability due to mapping on a PIM substrate, focusing on PIM architectures that perform logic operations directly within memory arrays, in-situ, obviating any need for data transfers (even to and from the array periphery), e.g., CRAM. Here we (i) quantitatively characterize gate–flip errors, an acute class of functional errors specific to such PIM systems, where, due to parametric variations, a logic gate can behave as another; and (ii) analyze to what extent algorithmic noise tolerance can mask gate-flips.

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