Design and Optimization of Low-Power and High-Speed Spintronic Logic Devices

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Design and Optimization of Low-Power and High-Speed Spintronic Logic Devices

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Modern silicon transistor-based electronic circuits dissipate tremendous amounts of power as heat during computation. This has proven to be a bottleneck in making faster and smaller circuits. The sizes of the transistors on a chip have halved while their density on chip has doubled every 1.5 – 2 years for the last 50 years along a trajectory referred to as Moore's law. However, Moore's law is now losing steam due to the limitations of MOS transistors–mainly high power dissipation, limiting the further scaling of the MOS transistors. Thus, there is a need to search for replacement of the MOS technology to meet the increasing need for faster and more powerful electronics. The field of spintronics is often spoken as the most promising technology in this regard. Spintronics exploits this spin degree of freedom in electrons to perform computation. In spin-based devices, information is encoded in the collective spin or the net magnetization of a small magnet. Logic and memory operation is performed by manipulating the magnetization using physical phenomena. Spintronics promises (a) a very low energy computation to switch the magnetization between the two binary values, (b) nonvolatility and (c) novel functionalities. The design of spintronic devices poses a great challenge as it involves knowledge of complex physical phenomena, properties of materials, and a general understanding of devices and circuits to build large-scale systems. Several spin-based devices have been proposed recently. However, none of these focuses on building devices that are optimized for maximum performance, such as delay and energy dissipation. Therefore, large scale circuits using spin-based devices perform poorly when compared against the MOS technology. This thesis attempts to tackle this issue by (a) proposing optimization techniques to improve the energy and delay of the existing spin-based devices and facilitate easy design of large spin-based chips, and (b) propose new spin-based devices and novel circuit techniques that aims to exploit the spin-based physical phenomena that promises low-power operation. One of the most widely researched spin-based logic device candidates is called all– spin logic (ASL). In this thesis, we use a systematic approach to build an optimized ASL standard cell library. The ASL standard cells can then be easily used to build large spin-based circuits. First, we propose a novel technique to reduce the magnet count for implementing the AND gate using majority logic. We develop compact layouts for each logic gate in the cell library and use physics–based models to obtain the delay and energy of the logic gates. At the gate level, our method results in up to 24% faster and up to 47% more energy–efficient logic gates. At the circuit level, our method synthesizes ASL circuits that are up to 13% faster and up to 26% more energy–efficient compared to their corresponding unoptimized counterparts. We extend the base ASL scheme and propose a novel circuit level technique, called STEM (Scheme for Two-phase Evaluation of Majority Logic) that could be applied to any majority gate-based circuits to further reduce the power consumption. Such a two-phased technique results in an overall lower magnet count and a 1.6x–3.4x faster and 1.9x–6.4x more power-efficient ASL gates as compared to the traditional ASL implementation. To be competitive with MOS, spintronic logic devices should be both fast and dissipate low power. With this goal in mind, in this thesis, we explore two alternative devices. The first is CoMET (Composite Input Magneto Electric Logic Technology), a magnetoelectric (ME) effect-based device, which has the potential for very low power device operation. We use physics–based models for the ME effect and domain walls to obtain the performance metrics of CoMET. We build a compact CoMET device and perform optimizations at (a) the device level over different material parameter combinations, and (b) the circuit–level for easy cascading of devices to obtain a 27× faster device at similar energy compared to existing ME devices. CoMET significantly outperforms MOS technology for energy-harvesting applications, by exploiting its nonvolatility. The second proposed device is based on skyrmions, which are magnetic vortex- like nanostructures that have shown promise due to their robustness to pinning in the magnetic films and their potential to be miniaturized to a diameter of a few nanometers. In this thesis, we present a skyrmion-based device, SkyLogic, and create a framework for analyzing its performance. We also propose a novel circuit technique to counter the transverse motion of the skyrmion along with its longitudinal motion which significantly increases the skyrmion propagation latencies, thereby incurring large device delay. We optimize the performance of the device over different material combinations to obtain an optimal design point. The last part of the thesis addresses the design of non-Boolean neuromorphic systems based on emerging spintronic devices. Advances in artificial intelligent systems have been primarily driven by the widespread adoption of neural networks. We explore the use of spiking neural networks (SNNs) that use information spikes to transmit information, much like the human brain. CMOS-based hardware to implement SNNs are not power efficient because of the data-intensive nature of the SNNs. We build a compact neuron hardware substrate for SNNs, which form the fundamental building block of a neural network. We then implement an all ferroelectric FET (FeFET)-based unsupervised winner-takes-all SNN and show how this platform can be used to perform handwritten digit recognition on the MNIST database. The procedure use FeFET models to tune the neuron behavior to increase the accuracy of the SNN. We show that our implementation results in a very high accuracy for a compact implementation of the FeFET-based SNN.


University of Minnesota Ph.D. dissertation. February 2020. Major: Electrical/Computer Engineering. Advisor: Sachin Sapatnekar. 1 computer file (PDF); xviii, 165 pages.

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Mankalale, Meghna. (2020). Design and Optimization of Low-Power and High-Speed Spintronic Logic Devices. Retrieved from the University Digital Conservancy,

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