Exploring a multiprocessor design space to analyze the impact of using STT-RAM in the memory hierarchy

Abstract

Spin-tronic memory is a promising technology and offers advantages due to its non-volatility and higher density. At the same time, based on device properties, there are trade-offs that decide the energy and performance penalty overhead. To decide these trade-offs its it imperative to understand the sensitivity of different parameters in the memory subsystem. In this work, we use a known statistical technique to analyze processor core and memory parameters for their sensitivity towards performance and energy for a Spin-tronic based memory hierarchy. We also study how does the sensitivity of processor core parameters like Re-order buffer, Load Store queue etc. vary when we replace a traditional SRAM memory with the new spin-tronic technology. Further, given a mix of different memory technologies and important processor core parameters, we use find the optimal configuration for delay, energy and area using the method of simulated annealing.