Browsing by Author "Jiang, Zhenzhen"

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    Performance Study of a Concurrent Multithreaded Processor
    (1997) Tsai, Jenn-Yuan; Jiang, Zhenzhen; Ness, Eric; Yew, Pen-Chung
    The performance of a concurrent multithreaded architectural model, called superthreading [15), is studied in this paper. It tries to integrate optimizing compilation techniques and run-time hardware support to exploit both thread-level and instruction-level parallelism, as opposed to exploit only instruction-level parallelism in existing superscalars. The superthreaded architecture uses a thread pipelining execution model to enhance the overlapping between threads, and to facilitate data dependence enforcement between threads through compiler-directed, hardwaresupported, thread-level control speculation and run-time data dependence checking. We also evaluate the performance of the superthreaded processor through a detailed trace-driven simulator. Our results show that the superthreaded execution model can obtain good performance by exploiting both thread-level and isntruction-level parallelism in programs. We also study the design parameters of its main system components, such as the size of the memory buffer, the bandwidth requirement of the communication links between thread processing units, and the bandwidth requirement of the shared data cache.
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    Performance Study of Superthreaded Architecture: A Thesis
    (1997) Jiang, Zhenzhen
    This paper presents the simulation studies done on the Superthreaded Architecture. Two trace-driven, cycle-by-cycle Superthreaded processor simulators are implemented for the study. One issues single instruction per thread in each clock cycle, (called SIPT Superthreaded Simulator in this paper), the other has Superscalar features incorporated into it and issues multiple instructions per thread in each clock cycle (called MIPT Superthreaded Simulator in this paper). Both allow run-time datadependence checking and instruction scheduling. The simulation results show that the Superthreaded architecture, which adopts a thread-pipelining execution model and allows threads with data dependencies and control dependencies to be executed in parallel, can handle loops with run-time control speculation very well, and can achieve good speedups for most of the SPEC benchmark programs. What's more, some design features of the existing single-threaded multiple-issue processor, such as Superscalar, can be added onto the Superthreaded architecture to further exploit instruction-level parallelism.
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    Superthreading: Integrating Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading
    (1997) Tsai, Jenn-Yuan; Jiang, Zhenzhen; Li, Zhiyuan; Lilja, David; Wang, Xin; Yew, Pen-Chung; Zheng, Bixia; Glamm, Robert
    As the number of transistors that can be integrated on a single chip continues to grow, it is important for computer architects to think beyond the traditional approaches of deeper pipelines and wider instruction issue units for improving performance. This single-threaded execution model limits these approaches to exploiting only the relatively small amount of instruction-level parallelism available in application programs. While integrating an entire multiprocessor onto a single chip is feasible, this architecture is limited to exploiting only relatively coarse-grained heavy-weight parallelism. We propose the superthreaded architecture as an excellent alternative for utilizing the large number of transistors that will become available on a single high-density chip. As a hybrid of a wideissue superscalar processor and a multiprocessor-on-a-chip, this new concurrent multithreading architecture can leverage the best of existing and future parallel hardware and software technologies. By incorporating speculation for control dependences and run-time checking of data dependences, the superthreaded architecture can exploit the multiple granularities of parallelism available in general-purpose application programs to reduce the execution time of a single program.