Performance Study of Superthreaded Architecture: A Thesis

Abstract

This paper presents the simulation studies done on the Superthreaded Architecture. Two trace-driven, cycle-by-cycle Superthreaded processor simulators are implemented for the study. One issues single instruction per thread in each clock cycle, (called SIPT Superthreaded Simulator in this paper), the other has Superscalar features incorporated into it and issues multiple instructions per thread in each clock cycle (called MIPT Superthreaded Simulator in this paper). Both allow run-time datadependence checking and instruction scheduling. The simulation results show that the Superthreaded architecture, which adopts a thread-pipelining execution model and allows threads with data dependencies and control dependencies to be executed in parallel, can handle loops with run-time control speculation very well, and can achieve good speedups for most of the SPEC benchmark programs. What's more, some design features of the existing single-threaded multiple-issue processor, such as Superscalar, can be added onto the Superthreaded architecture to further exploit instruction-level parallelism.