Superthreading: Integrating Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading
1997
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Superthreading: Integrating Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading
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1997
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Abstract
As the number of transistors that can be integrated on a single chip continues to grow, it is important
for computer architects to think beyond the traditional approaches of deeper pipelines and wider
instruction issue units for improving performance. This single-threaded execution model limits these
approaches to exploiting only the relatively small amount of instruction-level parallelism available
in application programs. While integrating an entire multiprocessor onto a single chip is feasible,
this architecture is limited to exploiting only relatively coarse-grained heavy-weight parallelism.
We propose the superthreaded architecture as an excellent alternative for utilizing the large number
of transistors that will become available on a single high-density chip. As a hybrid of a wideissue
superscalar processor and a multiprocessor-on-a-chip, this new concurrent multithreading
architecture can leverage the best of existing and future parallel hardware and software technologies.
By incorporating speculation for control dependences and run-time checking of data dependences,
the superthreaded architecture can exploit the multiple granularities of parallelism available in
general-purpose application programs to reduce the execution time of a single program.
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Tsai, Jenn-Yuan; Jiang, Zhenzhen; Li, Zhiyuan; Lilja, David; Wang, Xin; Yew, Pen-Chung; Zheng, Bixia; Glamm, Robert. (1997). Superthreading: Integrating Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/215316.
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