Future generation architectures and circuits for high-speed I/O Links
2010-06
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Future generation architectures and circuits for high-speed I/O Links
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2010-06
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Abstract
The persistent demand for increased data throughput in computer desktops and
servers has been driving the design and development of high-speed I/O links in CMOS
technologies. Frequency dependent channel loss and imperfections, such as impedance
discontinuities, in I/O transceiver building blocks lead to inter-symbol interference (ISI)
which limits the achievable link throughput. Crosstalk noise from neighboring channels
results in both timing and amplitude errors with the growing data rate trends in chip-tochip
communication. In addition, increasing ISI and crosstalk noise sources complicates
the design of critical circuit blocks such as timing recovery. All these factors exacerbate
the eye closure at the receiver and adversely affect the performance or bit-error-rate
(BER) of the overall link. This thesis extends the design scope of current high-speed
I/O systems by applying the joint know-how in advanced digital communication and
novel circuit implementations. Several architectures and schemes including equalization,
timing recovery and timing generation circuits are proposed which address some of the
limiting factors in today’s chip-to-chip I/O links.
First, partial response (PR) equalization is presented analyzed and demonstrated
as a successful candidate for steep roll-off channel classes. Based on this technique, a
transceiver with PR transmit equalizer and a 1-tap decision feedback equalizer (DFE) is
proposed which increases the signal to noise (SNR) of the received signal at the receiver
decision circuit input. The proposed PR1.1.b equalization in this thesis outperforms
duobinary signaling by 28% and 19% when comparing vertical eye opening and by 10% and 7% when comparing horizontal eye opening at 10Gbps and 15Gbps respectively.
These improvements become significantly higher when the channel is subjected to severe
crosstalk noise sources. Additionally this architecture mitigates the circuit design issue
related to tight DFE loop timing and convergence.
Second, a novel pilot-based clock and data recovery (CDR) circuit is introduced that
eliminates the clock recovery performance dependency on channel ISI components. A
5Gbps CDR prototype was designed and fabricated in a 0.13μm CMOS technology which
uses simultaneously data and clock transmission over the same channel. The measured
recovered clock rms jitter was 1.6ps while only a 5% voltage overhead was imposed onto
the transmitter for the pilot signal when subjected to a channel loss of 10dB.
Third, a 5.6GHz transmit phase-locked-loop (PLL), prototyped in a 0.18μm CMOS
technology, is also presented which dynamically corrects the charge-pump (CP) current
and reduces the side-band spurs by 22dB and therefore improves the jitter quality of the PLL generated clock.
Finally a unified configurable I/O transceiver solution is introduced that takes advantages
of all the architecture schemes and circuits proposed throughout the thesis for
future chip-to-chip communication ICs.
Description
University of Minnesota Ph.D. dissertation. June 2010. Major: Electrical engineering. Advisor: Professor Ramesh Harjani. 1 computer file (PDF); xiii, 115 pages, appendix A.
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Ahmadi, Mahmoud Reza. (2010). Future generation architectures and circuits for high-speed I/O Links. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/128074.
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