Three dimensional packaging is considered as a promising packaging solution that can offer small form factor and high performance capability to high- speed electronics, for instance, modern multi- functional wireless communication devices in which a variety of analog and digital circuits such as high performance computing functional blocks, image sensors, display unit, and multi-band radios is integrated. To implement this multi- functional device with excellent performance, seamless packaging strategies are required. To this end, this dissertation presents several 3D interconnects for wafer-level packaging and embedded passives in multi-layer substrates. A novel ultra- broadband flip-chip interconnect, referred to as locally matched flip-chip (LMFC) interconnect, is developed using silicon bulk micromachining for low profile solder bump pad. The LMFC interconnect offers a return loss below 20 dB over 96 % of the 2-110 GHz bandwidth with low insertion loss. Two silicon micromachined features, air cavity and trenches, enable the LMFC to operate up to W-band (75- 110 GHz). Through silicon via (TSV) is another 3D interconnect to replace wire bond interconnect. Two novel TSV interconnects, referred to as truncated GND TSV and trenched TSV interconnect, are presented for operation up to Q-band (33-50.5 GHz) and W-band. A simple truncation of ground plane in coplanar waveguide expands the operating bandwidth up to Q-band. Air trenches in the transition region with the truncation of ground plane make the TSV interconnect operate up to W-band. Time domain performance of the 3D interconnects is also presented. To gain insight of the novel 3D interconnects performance in time domain, eye- diagram analysis is performed on the 3D interconnects. The time domain performance of the 3D interconnects indicates that the novel designs improve significantly in amplitude variation and timing errors of the conventional counterparts. Miniaturization of passive circuit components remains challenging area. Embedded band pass filters (BPFs) in silicon and low temperature co-fired ceramic (LTCC) multi- layer substrates are designed and characterized. In silicon multi- layer substrate, air dielectric is integrated for enhancement of spiral inductor in the BPF design. TSV also plays a main role in the design. For further miniaturization, very thin ceramic layer is used in the LTCC version of the BPF design.
University of Minnesota Ph.D. dissertation.August 2010. Major: Electrical Engineering. Advisor: Rhonda Franklin. 1 computer file (PDF); xix 235 pages.
Cho, Young Seek.
Development of Three Dimensional Integration and Packaging Techniques for Complex Communication Systems.
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