Browsing by Subject "STT-MRAM"

Now showing 1 - 5 of 5
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    Advanced Simulation Techniques for Evaluating Emerging Magnetoresistive Random Access Memory Technologies for Next Generation Non-Volatile Memory
    (2020-08) Song, Jeehwan
    Magnetoresistive random access memory (MRAM) has various features such as nonvolatility, zero static power consumption, CMOS compatibility, and high endurance, which enable it to be a potential candidate for the next generation non-volatile memory (NVM) technology. The MRAM basically stores the data in a magnetic tunnel junction (MTJ) device which consists of a free ferromagnetic layer, an oxide barrier, and a fixed ferromagnetic layer, and the intrinsic properties of MTJ device have critical roles in write and read operations considering thermal fluctuation. Due to the importance of the MTJ device, the academic and industrial groups have researched the MTJ device models for reliable MRAM applications, however, there is still no standard model to be commonly utilized in design process. Moreover, diverse types of MRAM have been researched for the last few decades. For example, spin-transfer torque (STT)-MRAM, voltage-controlled magnetic anisotropy (VCMA)-MRAM, and spin-Hall effect (SHE)-MRAM have been evaluated in order to commercialize more effective MRAM application. STT-MRAM, which utilizes bidirectional current flow for switching, has almost reached commercialization with mass production. SHE-MRAM consists of MTJ with spin Hall metal (SHM) to generate efficient spin current, whereas the VCMA MRAM utilizes a VCMA effect to lower the energy barrier of magnetization for faster switching and lower energy consumption. This thesis has focused on different modeling approaches such as a SPICE-based compact model and a Fokker-Planck model for representative MRAM types. Using the simulation models, we provide practical analyses of the MRAM applications as well as comparison of the models. Firstly, SPICE-based MTJ compact model is introduced for the VCMA-MRAM application. For this study, we developed a physics-based SPICE model that includes various VCMA parameters such as VCMA coefficient, energy barrier time constant, and external magnetic field. Using realistic material and device parameters, we evaluate the operating margin and switching probability of the VCMA-MRAM. Based on the Monte-Carlo simulation, the highest switching probabilities were 94.9, 84.8, and 53.5 %, for VCMA coefficient values of 33, 105, and 290 fJ·V-1·m-1, respectively. For the practical memory applications, their switching probability must be improved by incorporating different physics. Secondly, the Fokker-Planck (FP) numerical model is utilized for an efficient analysis of STT-MRAM application, which allows for parametric variation and evaluates its impact on switching. We analyzes the impact of MTJ material and geometric parameter variations such as saturation magnetization (MS), magnetic anisotropy (HK), damping factor (α), spin polarization efficiency factor (η), oxide thickness (tOX), free layer thickness (tF), tunnel magnetoresistance (TMR), and cross-sectional area of free layer (AF) variations on Write Error Rate (WER) and Read Disturbance Rate (RDR) for reliable write and read operations. Both WER and RDR are analyzed with a wide range of MTJ diameters between 90nm and 30nm to evaluate the scalability of MRAM devices. Even though the effect of material and geometric parameter variations on WER is decreased as MTJ scales down, the variation effect can be still considerable with small MTJ diameter and the most significant influential variation is η, MS, HK, and α in that order. On the other hand, the impact of the parameter variations on RDR increases in MTJ scaling, and the negative variations of HK and MS could be major problems in 30nm and 40nm MTJ diameters. The efficient FP numerical model-based study puts emphasis on the need of WER and RDR analyses by considering the parameter variations in MTJ scaling for practical STT-MRAM development. Thirdly, MRAM applications have been also expected to replace embedded cache memories in the near future. For the MRAM-based embedded cache memory, precedent research considering MRAM’s high write current, scaling challenges, and variation issues should be studied. In this work, a physics based MTJ model are utilized to evaluate the scalability and variability of the MRAM based cache memory. Through the studies, we investigate STT and SHE MRAM based cache memory applications considering device, circuit, layout, and architecture level details.
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    Allocation policy analysis for cache coherence protocols for STT-MRAM-based caches
    (2014-10) Nandkar, Pushkar Shridhar
    Spintronic devices have demonstrated promising results to replace the traditional CMOS devices in Last Level Caches. Recent research have focussed on STT-CMOS hybrid caches and presented techniques to reduce leakage power and achieve performance benefit due to larger caches size that can be accommodated in the same footprint. Instead of using such hybrid caches, we use in-place STT-MRAM replacements for the complete cache hierarchy and show that we can achieve increased performance due to larger caches and significant power benefits due to decreased leakage. Further, we study different cache coherence protocols and with different allocation policies. Our preliminary results show that Non-inclusive protocols save write dynamic energy mostly due to reduced number of line fills compared to an inclusive protocol. We study the complete parsec benchmark suite and discuss the best allocation policy for each benchmark while considering the energy-delay trade off.
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    The Design of Spintronic-based Circuitry for Memory and Logic Units in Computer Systems
    (2018-10) Ma, Cong
    As CMOS technology starts to face serious scaling and power consumption issues, emerging beyond-CMOS technologies draw substantial attention in recent years. Spintronic device, one of the most promising CMOS alternatives, with smaller size and low standby power consumption, fits the needs of the trending mobile and IoT devices. Spin-Transfer Torque-MRAM (STT-MRAM) with comparable read latency with SRAM and All-spin logic (ASL) capable of implementing pure spin-based circuit are the potential candidates to replace CMOS memory and logic devices. However, spintronic memory continues to require higher write energy, presenting a challenge to memory hierarchy design when energy consumption is a concern. This motivates the use of STT-MRAM for the first level caches of a multicore processor to reduce energy consumption without significantly degrading the performance. The large STT-MRAM first-level cache implementation saves leakage power. And the use of small level-0 cache regains the performance drop due to the long write latency of STT-MRAM. This combination reduces the energy-delay product by 65% on average compared to CMOS baseline. All-spin logic suffers from random bit flips that significantly impacts the Boolean logic reliability. Stochastic computing, using random bit streams for computations, has shown low hardware cost and high fault-tolerance compared to the conventional binary encoding. It motivates the use of ASL in stochastic computing to take advantage of its simplicity and fault tolerance. Finite-state machine (FSM), a sequential stochastic computing element, can compute complex functions including the exponentiation and hyperbolic tangent functions more efficiently, but it suffers from long calculation latency and autocorrelation issues. A parallel implementation scheme of FSM is proposed to use an estimator and a dispatcher to directly initialize the FSM to the steady state. It shows equivalent or better results than the serial implementation with some hardware overhead. A re-randomizer that uses an up/down counter is also proposed to solve the autocorrelation issue.
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    Design techniques for dense embedded memory in advanced CMOS technologies
    (2012-02) Chun, Ki Chul
    On-die cache memory is a key component in advanced processors since it can boost micro-architectural level performance at a moderate power penalty. Demand for denser memories only going to increase as the number of cores in a microprocessor goes up with technology scaling. A commensurate increase in the amount of cache memory is needed to fully utilize the larger and more powerful processing units. 6T SRAMs have been the embedded memory of choice for modern microprocessors due to their logic compatibility, high speed, and refresh-free operation. However, the relatively large cell size and conflicting requirements for read and write make aggressive scaling of 6T SRAMs challenging in sub-22 nm. In this dissertation, circuit techniques and simulation methodologies are presented to demonstrate the potential of alternative options such as gain cell eDRAMs and spin-torque-transfer magnetic RAMs (STT-MRAMs) for high density embedded memories.Three unique test chip designs are presented to enhance the retention time and access speed of gain cell eDRAMs. Proposed bit-cells utilize preferential boostings, beneficial couplings, and aggregated cell leakages for expanding signal window between data `1' and `0'. The design space of power-delay product can be further enhanced with various assist schemes that harness the innate properties of gain cell eDRAMs. Experimental results from the test chips demonstrate that the proposed gain cell eDRAMs achieve overall faster system performances and lower static power dissipations than SRAMs in a generic 65 nm low-power (LP) CMOS process. A magnetic tunnel junction (MTJ) scaling scenario and an efficient HSPICE simulation methodology are proposed for exploring the scalability of STT-MRAMs under variation effects from 65 nm to 8 nm. A constant JC0*RA/VDD scaling method is adopted to achieve optimal read and write performances of STT-MRAMs and thermal stabilities for a 10 year retention are achieved by adjusting free layer thicknesses as well as projecting crystalline anisotropy improvements. Studies based on the proposed methodology show that in-plane STT-MRAM will outperform SRAM from 15 nm node, while its perpendicular counterpart requires further innovations in MTJ material properties in order to overcome the poor write performance from 22 nm node.
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    Spin-Based Logic and Memory Technologies for Low-Power Systems
    (2016-02) Kim, Jongyeon
    As the end draws near for Moore’s law, the search for low-power alternatives to CMOS technology is intensifying. Among the various post-CMOS candidates, spintronic devices have gained special attention due to its unique features such as zero static power, compact size, and instant wakeup, while enabling an entirely new class of architectures such as processor-in-memory, logic-in-memory, and neuromorphic computing. However, traditional spintronics research has been mainly limited to the materials and single device level, so the main aim of this dissertation is to clearly describe spin-based logic and memory technologies by exploring the trade-off points across different levels of design abstraction (i.e. device, circuit, and architecture). For spin-based logic, we benchmark the system-level capability of spin-logic technology using a hypothetical spintronic-based Intel Core i7 as a test vehicle. We describe how spin-based components are integrated into a computing system and the advantages that result. Even with early promises such as zero static power, lower device count, and lower supply voltage, technical barriers associated with spin devices such as low spin injection, limited spin diffusion length, and intrinsically high activity factor result in higher active power than CMOS. For spin-based memory, a key aspect of technology evaluation is the development of a reliable MTJ model, so we first propose a technology-agnostic MTJ model specifically designed for evaluating the scalability and variability of STT-MRAM circuits. Using the proposed model, we evaluate the circuit-level scalability of MTJ technologies providing the detailed scaling methods and projection scenarios down to 7nm. For use in high speed on-chip cache applications, we also explore the feasibility of non-traditional MRAMs such as spin-Hall effect (SHE) MRAM which provides superior switching efficiency. In addition to the spintronics research, a logic-compatible eflash-based neuromorphic core is designed to provide a highly efficient architecture for neural computing. We use a logic-compatible embedded flash memory to store synaptic weights to provide a simple implementation of restricted Boltzmann machine (RBM) which is a well-known neural algorithm for digit recognition. With the proposed current-based architecture, a neuron operation can be accomplished by simply comparing two currents corresponding to excitatory and inhibitory weights without large digital neuron circuits used in previous works.