Allocation policy analysis for cache coherence protocols for STT-MRAM-based caches

Abstract

Spintronic devices have demonstrated promising results to replace the traditional CMOS devices in Last Level Caches. Recent research have focussed on STT-CMOS hybrid caches and presented techniques to reduce leakage power and achieve performance benefit due to larger caches size that can be accommodated in the same footprint. Instead of using such hybrid caches, we use in-place STT-MRAM replacements for the complete cache hierarchy and show that we can achieve increased performance due to larger caches and significant power benefits due to decreased leakage. Further, we study different cache coherence protocols and with different allocation policies. Our preliminary results show that Non-inclusive protocols save write dynamic energy mostly due to reduced number of line fills compared to an inclusive protocol. We study the complete parsec benchmark suite and discuss the best allocation policy for each benchmark while considering the energy-delay trade off.