Browsing by Subject "SAR ADC"
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Item CMOS Reliability Characterization Techniques and Spintronics-Based Mixed-Signal Circuits(2015-09) Choi, Won HoPlasma-Induced Damage (PID) has been an important reliability concern for equipment vendors and fabs in both traditional SiO2 based and advanced high-k dielectric based processes. Plasma etching and ashing are extensively used in a typical CMOS back-end process. During the plasma steps, the metal interconnect, commonly referred to as an “antenna,” collects plasma charges and if the junction of the driver is too small to quickly discharge the node voltage, extra traps are generated in the gate dielectric of the receiver thereby worsening device reliability mechanisms such as Bias Temperature Instability (BTI) and Time Dependent Dielectric Breakdown (TDDB). The foremost challenge to an effective PID mitigation strategy is in the collection of massive TDDB or NBTI data within a short test time. In this dissertation, we have developed two array-based on-chip monitoring circuits for characterizing latent PID including (1) an array-based PID-induced TDDB characterization circuit and (2) a PID-induced BTI characterization circuit using the 65nm CMOS process. As the research interest on analog circuit reliability is increasing recently, a few studies analyzed the impact of short-term Vth shift, not a permanent Vth shift, on a Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) and revealed that even short-term Vth shifts in the order of 1mV by short stress pulse (e.g., 1μs) on the comparator input transistors may cause to degrade the resolution of the SAR ADC even for a fresh chip (no experimentally verified). In this dissertation, we quantified this effect through test-chip studies and propose two simple circuit approaches that can be used to mitigate short-term Vth instability issues in SAR ADCs. The proposed techniques were implemented in 10-bit SAR ADC using the 65nm CMOS process. Spintronic circuits and systems have several unique properties including inherent non-volatility that can be uniquely exploited for achievable functional capabilities not obtainable in conventional systems. Magnetic Tunnel Junction (MTJ) technology has matured to the point where commercial spin transfer torque MRAM (STT-MRAM) chips are currently being developed. This work aims at leveraging and complimenting on-going development efforts in MTJ technology for non-memory mixed-signal applications. In this dissertation, we developed two spintronics-based mixed-signal circuit designs: (1) an MTJ-based True Random Number Generator (TRNG) and (2) an MTJ-based ADC. The proposed TRNG and ADC have the potential to achieve a compact area, simpler design, and reliable operation as compared to their CMOS counterparts.Item Data Conversion Techniques for Next Generation Communications(2017-12) Saha, AnindyaThe voice-only mobile-telephony 1G systems have evolved a long way to today’s data-driven 4G LTE networks, causing an exponential increase in mobile broadband data consumption. Furthermore, 5G is expected to deliver unprecedented data rates (tens of Gbps) exploiting mm-wave bands (30-300 GHz). Analog-to-digital converters (ADC) are one of the crucial factors in determining the pursued data rates. In the first part of this dissertation, a 100MS/s 9-bit companding SAR ADC, which exploits the statistical properties to reduce the PAPR of broadband multi-carrier signals in 4G LTE has been investigated. The architecture provides amplitude-specific gain with a fast instantaneous AGC, reducing the effects of PAPR and optimizing quantization noise, emulating the performance of a higher resolution ADC. Additionally, gain-before-sampling results in reduced sampling capacitor size, which lowers power and area. In the second part of this dissertation, a 1 GS/s 7-bit ADC using PWM technique and time-domain quantization is investigated to harness the benefits of the rapidly improving time resolution, so that the envisioned data rates in 5G can be realized with the lowest possible power. Thanks to digital delay line based time-domain computations, proposed architecture is highly digital therefore scalable, which is beneficial since scaling does not favor voltage-domain circuits.Item Design of PVT Tolerant Inverter Based Circuits for Low Supply Voltages(2015-06) Palani, Rakesh KumarRapid advances in the field of integrated circuit design has been advantageous from the point of view of cost and miniaturization. Although technology scaling is advantageous to digital circuits in terms of increased speed and lower power, analog circuits strongly suffer from this trend. This is becoming a crucial bottle neck in the realization of a system on chip in scaled technology merging high-density digital parts, with high performance analog interfaces. This is because scaled technologies reduce the output impedance (gain) and supply voltage which limits the dynamic range (output swing). One way to mitigate the power supply restrictions is to move to current mode circuit circuit design rather than voltage mode designs. This thesis focuses on designing Process Voltage and Temperature (PVT) tolerant base band circuits at lower supply voltages and in lower technologies. Inverter amplifiers are known to have better transconductance efficiency, better noise and linearity performance. But inverters are prone to PVT variations and has poor CMRR and PSRR. To circumvent the problem, we have proposed various biasing schemes for inverter like semi constant current biasing, constant current biasing and constant gm biasing. Each biasing technique has its own advantages, like semi constant current biasing allows to select different PMOS and NMOS current. This feature allows for higher inherent inverter linearity. Similarly constant current and constant gm biasing allows for reduced PVT sensitivity. The inverter based OTA achieves a measured THD of -90.6 dB, SNR of 78.7 dB, CMRR 97dB, PSRR 61 dB wile operating from a nominal power of 0.9V and at output swing of 0.9V{pp,diff} in TSMC 40nm general purpose process. Further the measured third harmonic distortion varies approximately by 11.5dB with 120C variation in temperature and 9dB with a 18% variation in supply voltage. The linearity can be increased by increasing the loop gain and bandwidth in a negative feedback circuit or by increasing the over drive voltage in open loop architectures. However both these techniques increases the noise contribution of the circuit. There exist a trade off between noise and linearity in analog circuits. To circumvent this problem, we have introduced nonlinear cancellation techniques and noise filtering techniques. An analog-to-digital converter (ADC) driver which is capable of amplifying the continuous time signal with a gain of 8 and sample onto the input capacitor(1pF) of 1 10 bit successive approximation register (SAR) ADC is designed in TSMC 65nm general purpose process. This exploits the non linearity cancellation in current mirror and also allows for higher bandwidth operation by decoupling closed loop gain from the negative feedback loop. The noise from the out of band is filtered before sampling leading to low noise operation. The measured design operates at 100MS/s and has an OIP_3 of 40dBm at the nyquist rate, noise power spectral density of 17nV/sqrt{Hz} and inter modulation distortion of 65dB. The intermodulation distortion variation across 10 chips is 6dB and 4dB across a temperature variation of 120C. Non linearity cancellation is exploited in designing two filters, an anti alias filter and a continuously tunable channel select filter. Traditional active RC filters are based on cascade of integrators. These create multiple low impedance nodes in the circuit which results in a higher noise. We propose a real low pass filter based filter architecture rather than traditional integrator based approach. Further the entire filtering operation takes place in current domain to circumvent the power supply limitations. This also facilitates the use of tunable non linear metal oxide semiconductor capacitor (MOSCAP) as filter capacitors. We introduce techniques of self compensation to use the filter resistor and capacitor as compensation capacitor for lower power. The anti alias filter designed for 50MHz bandwidth is fabricated in IBM 65nm process achieves an IIP3 of 33dBm, while consuming 1.56mW from 1.2 V supply. The channel select filter is tunable from 34MHz to 314MHz and is fabricated in TSMC 65nm general purpose process. This filter achieves an OIP3 of 25.24 dBm at the maximum frequency while drawing 4.2mA from 1.1V supply. The measured intermodulation distortion varies by 5dB across 120C variation in temperature and 6.5dB across a 200mV variation in power supply. Further this filter presents a high impedance node at the input and a low impedance node at the output easing system integration. SAR ADCs are becoming popular at lower technologies as they are based on device switching rather than amplifying circuits. But recent SAR ADCs that have good energy efficiency have had relatively large input capacitance increasing the driver power. We present a 2X time interleaved (TI) SAR ADC which has the lowest input capacitance of 133fF in literature. The sampling capacitor is separated from the capacitive digital to analog converter (DAC) array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in charge domain. The proposed ADC is fabricated in TSMC's 65nm general purpose process and occupies an area of 0.0338 mm^2. The measured ADC spurious free dynamic range (SFDR) is 57dB and the measured effective number of bits (ENOB) at nyquist rate is 7.55 bit while using 1.55mW power from 1 V supply. A sub 1V reference circuit is proposed, that exploits the complementary to absolute temperature (CTAT) and proportional to absolute temperature (PTAT) voltages in the beta multiplier circuit to attain a stable voltage with temperature and power supply. A one-time calibration is integrated in the architecture to get a good performance over process. Chopper stabilization is employed to reduce the flicker noise of the reference circuit. The prototype was simulated in TSMC 65nm process and we obtain the nominal output of 236mW, while consuming 0.7mW from power supply. Simulations show a temperature coefficient of 18 ppmC from -40 to 100C and with a power supply ranging from 0.8 to 2V.Item A low power biosensor for medical applications(2014-08) Hu, Chia-LinThis research presents on a CMOS sensor, which includes a chopper stabilized front-end amplifier with DC suppressed feedback and a 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with background calibration. It could reduce the flicker noise interference in the low frequency and suppressed the DC offset voltage between the two input signals. Therefore, this structure is suitable for bio-medical applications. The bio-medical signals are smaller than 5 mV in the low frequency between 0.01 Hz and 1 kHz. After amplifying, the signals will be digitized by a 12-bit SAR ADC.The chopper stabilized amplifier has a clock rate, 16 kHz, controlling the chopper switches and shifting the original signals to 16 kHz in order to reducing the flicker noise. In our case, the flicker noise could lower at least 80 times at this clock rate. The two-Thomas Biquad low-pass filter, as the anti-aliasing filter, could suppress the harmonic signals at least 40dB before digitalized by ADC. For the 12-bit SAR ADC, the differential nonlinearity (DNL) is +0.576/-0.96 least significant bit (LSB), and the integral nonlinearity (INL) is +0.534/-0.655 LSB. The signal-to-noise and distortion ratio (SNDR) can be estimated 69dB. The effective number of bits (ENOB) is 11.17. The total power dissipation of the ADC is 60-µW at 500-KS/s sampling rate and the supply voltages are ±0.5V. The figure of merit (FOM) is 52.08-fJ/conversion step.