Browsing by Subject "Power delivery"

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    Circuit modeling and design techniques for efficient power delivery under resonant supply noise
    (2011-07) Jiao, Dong
    Power supply noise has become one of the main performance limiting factors in sub-1V technologies. Resonant supply noise caused by the package/bonding inductance and on-die capacitance has been reported as the dominant supply noise component in high performance microprocessors. Recently, adaptive clocking schemes have been proposed to mitigate the impact of resonant noise. Here, the clock period is intentionally modulated by the resonant noise when it is generated in PLL or propagates through the clock distribution. As a result, the increased clock period partially compensates for the increased datapath delay which is also modulated by the same resonant noise and this is called clock data compensation effect, or beneficial jitter effect. This thesis presents a comprehensive study of this clock data compensation effect including an analysis of its dependency on various design parameters. A mathematical framework, including both an analytical model and a numerical model, is also proposed to accurately describe this timing compensation effect. To achieve optimal timing compensation, a certain amount of phase shift and proper adjustment of the clock period's sensitivity to supply noise are required. Here we also propose phase-shifted clock distribution designs and an adaptive phase-shifting PLL design to enhance the beneficial clock data compensation effect. Compared with conventional approaches, the proposed phase-shifted clock distribution designs save 85% of the clock buffer area while achieving a similar amount of improvement in the maximum operating frequency (Fmax) for typical pipeline circuits. In the proposed adaptive phase-shifting PLL, both the phase shift and the supply noise sensitivity of the clock can be digitally programmed and adjusted so that the optimal compensation can always be achieved under different conditions. Two test chips were fabricated in a 65nm CMOS process for concept verification. Measurement results demonstrate that the proposed phase-shifted clock distribution designs can provide an 8-27% performance improvement in Fmax for typical resonant noise frequencies from 100MHz to 300MHz and the proposed phase-shifting PLL can provide 3-7% improvement in Fmax under various operating conditions.
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    Interconnect design techniques for multicore and 3D Integrated circuits.
    (2012-08) Zhou, Pingqiang
    Over the past 40 years, the semiconductor industry has witnessed the exponential growth trend in system complexity as predicted by Moore’s law, facilitated by continuously shrinking transistor and wire dimensions. Three dimensional (3D) circuit technology, with multiple tiers of active devices stacked above each other, is a key approach to achieve increasing levels of integration and performance in the future. Concomitant with exponentially reducing device dimensions, designers face new challenges in maximizing computation while remaining with a stringent power envelope. Over the last decade, multicore processors have emerged as a potential solution to address some of these problems by integrating multiple smaller and more energy efficient cores in order to replace a single, larger core. These cores must communicate through an efficient onchip interconnection network, by ideas such as networks-on-chips (NoCs), and NoC design is vital to both performance and power. This thesis presents solutions to the challenges in on-chip interconnect, more specifically, the on-chip communication and power delivery network of 3D and multicore chips. The first part of this thesis focuses on developing techniques for designing efficient and high-performance NoC architecture for 3D and multicore chips. Depending on the nature of the application, the multicore system may be either a System-on-Chip (SoC), which executes a relatively well-characterized workload, or a Chip multiprocessor (CMP), which is a general purpose processor that should be capable of handling a variety of workloads. For SoCs, this thesis presents an efficient algorithm to synthesize application-specific NoC architectures in a 3D environment. We demonstrate that this method finds greatly improved solutions compared to a baseline algorithm reflecting prior work. We also study the impact of various factors on the network performance in 3D NoCs, including the through-silicon via (TSV) count and the number of 3D tiers. For CMPs, we observe that voltage and frequency scaling (VFS) for NoC can potentially reduce energy consumption, but the associated increase in latency and degradation in throughput limits its deployment. Therefore, we propose flexible-pipeline routers that reconfigure pipeline stages upon VFS, so that latency through such routers remains constant. With minimal hardware overhead, the deployment of such routers allows us to reduce network frequency and save network energy, without significant performance degradation. The second part of this thesis is concerned with the design and optimization of power delivery network for 3D and multicore chips. First, we propose a novel paradigm where we exploit a new type of capacitor, the metal-insulator-metal (MIM) capacitor, together with the traditional CMOS decaps, to optimize the power supply noise in 3D chips. Experimental results show that power grid noise can be more effectively optimized after the introduction of MIM decaps, with lower leakage power and little increase in the routing congestion, as compared to a solution using CMOS decaps only. Second, we explore the design and optimization of on-chip switched-capacitor (SC) DCDC converters for multicore processors. On one hand, with an accurate power grid simulator, we find that distributed design of SC converters can reduce the IR drop significantly compared to the lumped design, with improved supply voltage. On the other hand, the efficiency of the power delivery system using SC converters is a major concern, but this has not been addressed at the system level in prior research. We develop models for the efficiency of such a system as a function of size and layout of the SC converters, and propose an approach to minimize power loss by optimizing the size and layout of the SC converters . The efficiency of these techniques is demonstrated on both homogenous and heterogenous multicore chips.