Circuit modeling and design techniques for efficient power delivery under resonant supply noise
2011-07
Loading...
View/Download File
Persistent link to this item
Statistics
View StatisticsJournal Title
Journal ISSN
Volume Title
Title
Circuit modeling and design techniques for efficient power delivery under resonant supply noise
Authors
Published Date
2011-07
Publisher
Type
Thesis or Dissertation
Abstract
Power supply noise has become one of the main performance limiting factors in sub-1V technologies. Resonant supply noise caused by the package/bonding inductance and on-die capacitance has been reported as the dominant supply noise component in high performance microprocessors. Recently, adaptive clocking schemes have been proposed to mitigate the impact of resonant noise. Here, the clock period is intentionally modulated by the resonant noise when it is generated in PLL or propagates through the clock distribution. As a result, the increased clock period partially compensates for the increased datapath delay which is also modulated by the same resonant noise and this is called clock data compensation effect, or beneficial jitter effect. This thesis presents a comprehensive study of this clock data compensation effect including an analysis of its dependency on various design parameters. A mathematical framework, including both an analytical model and a numerical model, is also proposed to accurately describe this timing compensation effect. To achieve optimal timing compensation, a certain amount of phase shift and proper adjustment of the clock period's sensitivity to supply noise are required. Here we also propose phase-shifted clock distribution designs and an adaptive phase-shifting PLL design to enhance the beneficial clock data compensation effect. Compared with conventional approaches, the proposed phase-shifted clock distribution designs save 85% of the clock buffer area while achieving a similar amount of improvement in the maximum operating frequency (Fmax) for typical pipeline circuits. In the proposed adaptive phase-shifting PLL, both the phase shift and the supply noise sensitivity of the clock can be digitally programmed and adjusted so that the optimal compensation can always be achieved under different conditions. Two test chips were fabricated in a 65nm CMOS process for concept verification. Measurement results demonstrate that the proposed phase-shifted clock distribution designs can provide an 8-27% performance improvement in Fmax for typical resonant noise frequencies from 100MHz to 300MHz and the proposed phase-shifting PLL can provide 3-7% improvement in Fmax under various operating conditions.
Description
University of Minnesota Ph.D. dissertation. July 2011. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); viii, 76 pages.
Related to
Replaces
License
Collections
Series/Report Number
Funding information
Isbn identifier
Doi identifier
Previously Published Citation
Suggested citation
Jiao, Dong. (2011). Circuit modeling and design techniques for efficient power delivery under resonant supply noise. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/155879.
Content distributed via the University Digital Conservancy may be subject to additional license and use restrictions applied by the depositor. By using these files, users agree to the Terms of Use. Materials in the UDC may contain content that is disturbing and/or harmful. For more information, please see our statement on harmful content in digital repositories.