Browsing by Subject "PLL"

Now showing 1 - 3 of 3
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    Advanced architectures for next generation wireless integrated circuits.
    (2009-06) Cai, Liuchun
    In this thesis, we present and discuss two advanced architectures of wireless integrated circuits. In the first part of this thesis we will focus on the design of an inductorless receiver, which include a LNA, mixer and frequency synthesizer. Inductors are used in RF design to extend the bandwidth by resonating out the load and/or parasitic capacitance. However, on-chip inductors are large and cannot be ported easily from one process to the next. Due to modern CMOS scaling, inductorless RF design is rapidly becoming possible. In this thesis we describe a new methodology for designing the RF frontends necessary for the wideband 1GHz-10GHz bandwidth in a 0.13um CMOS technology. To validate our design methodology two receiver RF frontends were designed; a traditional inductor based design and an inductorless design. A common-gate LNA transconductor is followed by a capacitive peaking LNA-mixer pair (CPLM). Measurement results indicate that CPLM with the same bandwidth has better linearity, comparable noise figure and uses only 17% more power. The silicon area for the CPLM is only 22% of the IPLM. Both designs can be mated with an inductorless, ring-oscillator based, wide lock range and low power PLL also shown in this thesis. We present theory and prototype results for injection-locked frequency dividers based on differential ring oscillators (D-ILFD) and single-ended ring oscillators (S-ILFD), which can be locked to all harmonics (i.e., even and odd). We have developed a general theory for lock range and phase noise for all harmonics for both topologies. Measurement results for the D-ILFD and the S-ILFD show that the lock range decreases with increasing harmonics at the low harmonics while leveling off for larger division ratios. Measured integrated phase noise for D-ILFD and S-ILFD also show that the integrated phase noise decreases with increasing harmonics. The measurement results corroborate our theory. Ring oscillator based D-ILFDs and S-ILFDs are compact and consume low power making them well suited for wideband low power PLLs. We exploit the ring VCO based on an updated Maneatis delay cell with self- boosted biased techniques, which has a ultra wide tuning range of 1 GHz to 10.3GHz. The injection-locked frequency divider (ILFD), which can lock to all harmonics, has been used. A wide lock range, low power PLL based ring VCO and ILFD has been designed for UWB radio. Experimental results indicate that integrated phase noise is below a 30 and power consumption is only 8.6 mA to 22.35 mA for the entire frequency bands. In the second part of this thesis, we focus on noise isolation for mixed-signal (RF/analog/digital) design in CMOS 3D ICs. Faraday cages have traditionally been used to provide isolation from electromagnetic fields. In this thesis, we describe the use of Faraday cages for reducing crosstalk in 3D ICs. We validate our methodology with a combination of simulation and measurements from fabricated prototype designs. Measurement and simulation results show that the crosstalk between the transmitter and receiver reduces by about 75dB up to 10GHz by using a Faraday cage in combination with tier-to-tier isolation, which is one of best performance reported so far. Measurement results indicate that the Faraday cages have no effect on the S-parameters and linearity of inductorless RF circuits. We further develop a lumped equivalent model for crosstalk with and without a Faraday cage. There is good agreement between measurement, 3D electromagnetic simulation and lumped circuit simulation.
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    Future generation architectures and circuits for high-speed I/O Links
    (2010-06) Ahmadi, Mahmoud Reza
    The persistent demand for increased data throughput in computer desktops and servers has been driving the design and development of high-speed I/O links in CMOS technologies. Frequency dependent channel loss and imperfections, such as impedance discontinuities, in I/O transceiver building blocks lead to inter-symbol interference (ISI) which limits the achievable link throughput. Crosstalk noise from neighboring channels results in both timing and amplitude errors with the growing data rate trends in chip-tochip communication. In addition, increasing ISI and crosstalk noise sources complicates the design of critical circuit blocks such as timing recovery. All these factors exacerbate the eye closure at the receiver and adversely affect the performance or bit-error-rate (BER) of the overall link. This thesis extends the design scope of current high-speed I/O systems by applying the joint know-how in advanced digital communication and novel circuit implementations. Several architectures and schemes including equalization, timing recovery and timing generation circuits are proposed which address some of the limiting factors in today’s chip-to-chip I/O links. First, partial response (PR) equalization is presented analyzed and demonstrated as a successful candidate for steep roll-off channel classes. Based on this technique, a transceiver with PR transmit equalizer and a 1-tap decision feedback equalizer (DFE) is proposed which increases the signal to noise (SNR) of the received signal at the receiver decision circuit input. The proposed PR1.1.b equalization in this thesis outperforms duobinary signaling by 28% and 19% when comparing vertical eye opening and by 10% and 7% when comparing horizontal eye opening at 10Gbps and 15Gbps respectively. These improvements become significantly higher when the channel is subjected to severe crosstalk noise sources. Additionally this architecture mitigates the circuit design issue related to tight DFE loop timing and convergence. Second, a novel pilot-based clock and data recovery (CDR) circuit is introduced that eliminates the clock recovery performance dependency on channel ISI components. A 5Gbps CDR prototype was designed and fabricated in a 0.13μm CMOS technology which uses simultaneously data and clock transmission over the same channel. The measured recovered clock rms jitter was 1.6ps while only a 5% voltage overhead was imposed onto the transmitter for the pilot signal when subjected to a channel loss of 10dB. Third, a 5.6GHz transmit phase-locked-loop (PLL), prototyped in a 0.18μm CMOS technology, is also presented which dynamically corrects the charge-pump (CP) current and reduces the side-band spurs by 22dB and therefore improves the jitter quality of the PLL generated clock. Finally a unified configurable I/O transceiver solution is introduced that takes advantages of all the architecture schemes and circuits proposed throughout the thesis for future chip-to-chip communication ICs.
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    Surface Treatment to Promote Endothelialization, UROP Summer 2022
    (2022-10) Hruby, Lukas
    This project analyzed the use of new surface coatings on tissue culture plastic to determine whether the proposed coating material would act as an effective alternative to endothelialization on TCP. The main method involved seeding cells onto 18 total TCP well plates, all with varying concentrations. Nine of the plates had fibronectin applied first, followed by the application of Poly-L-Lysine, with the other nine reversing the order. Based on the results, the plates that had Poly-L-lysine applied first had better overall cell count, and subsequently adhesion, than the plates with fibronectin first. Further experimentation must be done to determine whether the combination of substrates is overall more effective than solely using one substrate to complete endothelialization. This project outlines the importance of forming a monolayer of endothelial cells and is the first step to eventually synthesizing a completely biological transplant organ.