Browsing by Subject "MRAM"

Now showing 1 - 4 of 4
  • Thumbnail Image
    Item
    CMOS Ising Processor and Spintronic Memory Solution: From Concept to Implementation
    (2020-05) Ahmed, Ibrahim
    CMOS based information technology is facing two challenges simultaneously. The first challenge is efficiently solving the increasingly complex problems we are facing every day. Combinatorial optimization problems (COPs) are one such widely used complex problems. Real-world applications such as supply chain management, logistics control, transportation system design, communication network design, and VLSI layout optimization can be mapped to COP. The computational complexity of many of these COPs is NP-complete, NP-hard, or worse. The computation time for finding the optimal or near-optimal solution increases exponentially with the number of variables for a conventional von Neumann computer. This becomes a fundamental bottleneck for the large problem sizes that are associated with real-world problems. The second challenge is that the CMOS technology that powers all our computing devices reaches its physical limits resulting in the slow growth of computing power. Our data- and computation-driven society increasingly demand more computationally powerful and energy-efficient devices. The recent slow growth CMOS technology has driven the research for an alternative technology to replace some or all of CMOS technology. We explored two potential solutions to address the challenges mentioned above. A non-traditional computing method, Ising computer, have shown to solve COPs very efficiently with a small area and energy consumption. In this thesis, we explored a dedicated hardware accelerator based on CMOS Ising computer to address COPs. On the other hand, spintronic devices are a promising alternative to silicon-based CMOS technology. The spintronic memory applications have shown a lot of promise in recent years. We analyzed various competing spin-based memory write schemes and considered the viability of a spintronic memory solution in this thesis. We designed three CMOS Ising computers with an increasing number of spins and features to progress towards a dedicated Ising processor aiming to solve COPs. We designed electrically coupled CMOS ring oscillators as the network of spins, and studied various architectures and coupling mechanisms in this work. Our proof-of-concept design had six CMOS spins coupled with pseudoresistors. The pseudoresistors were controlled using digitally programmable digital to analog converters (DAC). We successfully mapped and solved NP-hard max-cut problems with an average accuracy of 91%, proving the feasibility of a CMOS Ising computer. However, the DAC circuits required prohibitively large current for a larger Ising computer. Additionally, the all-to-all connected architecture was not modular, and the layout complexity was too high for a practical hardware accelerator with hundreds or thousands of spins. Our second Ising computer was designed with 560 spins coupled using a digital latch based coupling. We found that the Ising computer was probabilistically exploring different local minima with similar quality solutions. The probabilistic nature of the Ising computer is essential to solving difficult COPs. We mapped and solved 1000 graph problems in our chip with an accuracy of 82%-100% compared to the solution of a commercial COP solver. Our Ising computer was 10^4-10^6 times faster than the software with four orders of magnitude smaller energy requirement. Additionally, our experiments showed the Ising computer solutions are very consistent at various temperatures and supply voltage conditions. The measured results proved CMOS Ising computer is an excellent candidate for a hardware accelerator. Our third Ising computer was designed with 2150 spins coupled using a pass-gate based coupling which included multi-bit resolution coupling and local field bias. The proposed Ising computer can solve even more diverse and complex problems with the added features. Additionally, we designed a global coupling strength control to achieve better annealing to improve the solution quality. Our preliminary results show the Ising computer can solve difficult problems with an accuracy of 95%-100%. For our spintronic memory work, we developed a universal SPICE model for various MTJ write mechanisms, including spin-transfer torque (STT) and spin hall effect (SHE). We ran Monte-Carlo simulations using realistic magnetic and geometric parameters. The simulations showed SHE is less susceptible to thermal fluctuation than STT. SHE-only switching with a larger write current showed 8x and 7x delay and energy reduction, respectively. On the other hand, SHE-assisted STT switching showed 2x and 3x delay and energy reduction, respectively, with a smaller current requirement. Our analysis indicates SHE-assisted STT scheme can be a viable candidate for embedded applications, including the Ising computer.
  • Thumbnail Image
    Item
    Materials Research for High Efficiency Spin Orbit Torque Plus Voltage Controlled Magnetic Anisotropy Magnetoresistive Random-Access Memory
    (2022-05) peterson, thomas
    Current magnetoresistive random-access memory (MRAM) products utilize spin-transfer torque (STT) writing which requires large critical current densities, limiting the device lifetime as these large currents are forced through the tunneling barrier. Spin-orbit torque (SOT)-MRAM is a promising alternative to STT that circumvents many of STT’s issues by generating spin currents in a spin orbit torque channel under the free layer without interacting with the tunneling barrier. Decreasing the power consumption of SOT-MRAM requires materials with large spin torque efficiencies and low resistivities, such as heavy metals and topological semi-metals. A further decrease in power consumption can be realized by utilizing the voltage controlled magnetic anisotropy (VCMA) effect, which allows for a dynamic reduction in magnetic anisotropy with an applied voltage, lowering the switching energy while retaining high anisotropy for thermal stability. However, typical MTJ material stacks have shown minimal linear VCMA responses. Recent theoretical works have predicted a large and bidirectional VCMA effect at high levels of electron depletion, however, the required voltages to achieve these levels of depletion are beyond the dielectric breakdown of experimental gates. Inserting high work-function materials underneath the magnetic layer will deplete electrons from the magnetic layer, creating a built-in bias voltage. This can shift the gating window into the electron-depleted regime where the pJ/Vm and bidirectional VCMA effect was predicted.
  • Thumbnail Image
    Item
    Micromagnetic analysis of co-based magnetic nanostructures.
    (2010-12) Hernandez, Stephanie
    Micromagnetic analysis was employed in order predict the dynamical behavior of a variety of magnetic structures utilized in information storage devices. First, the surprising behavior of homogeneous perpendicular recording media was micromagnetically investigated. It is common to model recording media as interacting coherently rotating magnetic moments, but real materials frequently exhibit perpendicular switching fields less than the anisotropy field and a different angular dependence than theoretically expected. Micromagnetic simulations were performed, which included multiple elements per grain and magnetostatic interactions between elements. Two likely explanations have emerged from this analysis: the existence of low anisotropy regions within the first few atomic layers of the sputtered film or anisotropy gradation throughout the grain thickness. Both explanations offer appropriate coercivity reductions; however, grains including anisotropy gradation display this effect at more realistic values of intragranular exchange. Secondly, the lack of inclusion of spin-dependent scattering effects in most micromagnetic studies was addressed in this work. An analytic expression that includes the effect of multiple reflections within the interface of a tri-layer spin-valve composed of materials with partial spin polarization was obtained. Inclusion of this term in a micromagnetic calculation demonstrates the effect of the spin polarization of the magnetic material on the current induced behavior of the structure. We show that neglecting to include interfacial scattering events results in an underestimation of the switching current compared to the method detailed in this thesis. Multiple reflections also produce a strong dependence of the switching current on the magnetocrystalline anisotropy of the fixed layer. This approach was then extended to structures consisting of more than two ferromagnetic layers. Micromagnetic calculations employing this method achieved good agreement with electrical measurements performed on Co/Cu multilayer nanowire arrays.
  • Thumbnail Image
    Item
    Spintronics Devices for Advanced Memory and Computing Applications
    (2021-06) Zhao, Zhengyang
    Spintronics, as a beyond-CMOS technology, provides many possibilities for the next-generation information storage and processing. This thesis focuses on the development of novel spintronics devices towards low-energy, high-performance memory and computing applications. In this thesis, we present the manipulation of a magnetic storage unit either with a current-induced spin-orbit torque (SOT) or using a voltage via piezoelectric strain. We also propose a novel in-memory computing architecture based on the SOT storage cell. For the first part, the SOT induced switching is explored for both ferromagnets (FM) and antiferromagnets (AFM) systems. For the study of FM, two fundamental limitations related to the switching of a perpendicular magnetized system are solved. First, this thesis expands the scope of spin torque switchable materials, from interfacial PMA magnets only, to bulk PMA magnets, which have a better thermal stability when scaled down and are regarded as potential candidates in future MRAM. Second, the difficulty of field-free SOT switching is addressed by developing a dipole-coupled composite device. Compared with competitive strategies, the composite device is the most compatible one with existing MRAM technologies and readily applicable for SOT-based memory and logic devices. Beyond the exploration of SOT in FM, this thesis also attempts to tackle the spin torque induced switching in an AFM system, by characterizing the devices with a widely adopted 8-terminal geometry. It is discovered the “saw-tooth” signal, which was previously regarded as the evidence of AFM switching, actually originates from thermal artifacts. Then, the voltage-controlled device is studied utilizing a piezoelectric / magnetic tunnel junction (MTJ) coupled structure for ultra-low power writing of data. Voltage-controlled toggling of MTJ is achieved via the piezoelectric strain generated from a pair of local gates. The local gating design allows efficient manipulation of individual cells and opens the door towards realistic strain-based MRAM. Finally, a new architecture for computational random-access memory (CRAM) is invented based on the 3-terminal SOT-MTJ. Similar to the STT-MTJ based counterpart, the SOT-CRAM allows true in-memory computing and thereby meets the energy and throughput requirements of modern data-intensive processing tasks. Moreover, the excellent features of SOT unit cells would provide a large improvement in speed and energy compared with other in-memory computing paradigms.