CMOS Ising Processor and Spintronic Memory Solution: From Concept to Implementation
2020-05
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CMOS Ising Processor and Spintronic Memory Solution: From Concept to Implementation
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2020-05
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CMOS based information technology is facing two challenges simultaneously. The first challenge is efficiently solving the increasingly complex problems we are facing every day. Combinatorial optimization problems (COPs) are one such widely used complex problems. Real-world applications such as supply chain management, logistics control, transportation system design, communication network design, and VLSI layout optimization can be mapped to COP. The computational complexity of many of these COPs is NP-complete, NP-hard, or worse. The computation time for finding the optimal or near-optimal solution increases exponentially with the number of variables for a conventional von Neumann computer. This becomes a fundamental bottleneck for the large problem sizes that are associated with real-world problems. The second challenge is that the CMOS technology that powers all our computing devices reaches its physical limits resulting in the slow growth of computing power. Our data- and computation-driven society increasingly demand more computationally powerful and energy-efficient devices. The recent slow growth CMOS technology has driven the research for an alternative technology to replace some or all of CMOS technology. We explored two potential solutions to address the challenges mentioned above. A non-traditional computing method, Ising computer, have shown to solve COPs very efficiently with a small area and energy consumption. In this thesis, we explored a dedicated hardware accelerator based on CMOS Ising computer to address COPs. On the other hand, spintronic devices are a promising alternative to silicon-based CMOS technology. The spintronic memory applications have shown a lot of promise in recent years. We analyzed various competing spin-based memory write schemes and considered the viability of a spintronic memory solution in this thesis. We designed three CMOS Ising computers with an increasing number of spins and features to progress towards a dedicated Ising processor aiming to solve COPs. We designed electrically coupled CMOS ring oscillators as the network of spins, and studied various architectures and coupling mechanisms in this work. Our proof-of-concept design had six CMOS spins coupled with pseudoresistors. The pseudoresistors were controlled using digitally programmable digital to analog converters (DAC). We successfully mapped and solved NP-hard max-cut problems with an average accuracy of 91%, proving the feasibility of a CMOS Ising computer. However, the DAC circuits required prohibitively large current for a larger Ising computer. Additionally, the all-to-all connected architecture was not modular, and the layout complexity was too high for a practical hardware accelerator with hundreds or thousands of spins. Our second Ising computer was designed with 560 spins coupled using a digital latch based coupling. We found that the Ising computer was probabilistically exploring different local minima with similar quality solutions. The probabilistic nature of the Ising computer is essential to solving difficult COPs. We mapped and solved 1000 graph problems in our chip with an accuracy of 82%-100% compared to the solution of a commercial COP solver. Our Ising computer was 10^4-10^6 times faster than the software with four orders of magnitude smaller energy requirement. Additionally, our experiments showed the Ising computer solutions are very consistent at various temperatures and supply voltage conditions. The measured results proved CMOS Ising computer is an excellent candidate for a hardware accelerator. Our third Ising computer was designed with 2150 spins coupled using a pass-gate based coupling which included multi-bit resolution coupling and local field bias. The proposed Ising computer can solve even more diverse and complex problems with the added features. Additionally, we designed a global coupling strength control to achieve better annealing to improve the solution quality. Our preliminary results show the Ising computer can solve difficult problems with an accuracy of 95%-100%. For our spintronic memory work, we developed a universal SPICE model for various MTJ write mechanisms, including spin-transfer torque (STT) and spin hall effect (SHE). We ran Monte-Carlo simulations using realistic magnetic and geometric parameters. The simulations showed SHE is less susceptible to thermal fluctuation than STT. SHE-only switching with a larger write current showed 8x and 7x delay and energy reduction, respectively. On the other hand, SHE-assisted STT switching showed 2x and 3x delay and energy reduction, respectively, with a smaller current requirement. Our analysis indicates SHE-assisted STT scheme can be a viable candidate for embedded applications, including the Ising computer.
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University of Minnesota Ph.D. dissertation. 2020. Major: Electrical Engineering. Advisor: Chris Kim. 1 computer file (PDF); 146 pages.
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Ahmed, Ibrahim. (2020). CMOS Ising Processor and Spintronic Memory Solution: From Concept to Implementation. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/241358.
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