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Browsing by Subject "Digital Intensive"

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    Digital Intensive Mixed Signal Circuits with In-situ Performance Monitors
    (2016-11) Kundu, Somnath
    Digital intensive circuit design techniques of different mixed-signal systems such as data converters, clock generators, voltage regulators etc. are gaining attention for the implementation of modern microprocessors and system-on-chips (SoCs) in order to fully utilize the benefits of CMOS technology scaling. Moreover different performance improvement schemes, for example, noise reduction, spur cancellation, linearity improvement etc. can be easily performed in digital domain. In addition to that, increasing speed and complexity of modern SoCs necessitate the requirement of in-situ measurement schemes, primarily for high volume testing. In-situ measurements not only obviate the need for expensive measurement equipments and probing techniques, but also reduce the test time significantly when a large number of chips are required to be tested. Several digital intensive circuit design techniques are proposed in this dissertation along with different in-situ performance monitors for a variety of mixed signal systems. First, a novel beat frequency quantization technique is proposed in a two-step VCO quantizer based ADC implementation for direct digital conversion of low amplitude bio- potential signals. By direct conversion, it alleviates the requirement of the area and power consuming analog-frontend (AFE) used in a conventional ADC designs. This prototype design is realized in a 65nm CMOS technology. Measured SNDR is 44.5dB from a 10mVpp, 300Hz signal and power consumption is only 38μW. Next, three different clock generation circuits, a phase-locked loop (PLL), a multiplying delay-locked loop (MDLL) and a frequency-locked loop (FLL) are presented. First a 0.4-to-1.6GHz sub-sampling fractional-N all digital PLL architecture is discussed that utilizes a D-flip-flop as a digital sub-sampler. Measurement results from a 65nm CMOS test-chip shows 5dB lower phase noise at 100KHz offset frequency, compared to a conventional architecture. The Digital PLL (DPLL) architecture is further extended for a digital MDLL implementation in order to suppress the VCO phase noise beyond the DPLL bandwidth. A zero-offset aperture phase detector (APD) and a digital- to-time converter (DTC) are employed for static phase-offset (SPO) cancellation. A unique in-situ detection circuitry achieves a high resolution SPO measurement in time domain. A 65nm test-chip shows 0.2-to-1.45GHz output frequency range while reducing the phase-noise by 9dB compared to a DPLL. Next, a frequency-to-current converter (FTC) based fractional FLL is proposed for a low accuracy clock generation in an extremely low area for IoT application. High density deep-trench capacitors are used for area reduction. The test-chip is fabricated in a 32nm SOI technology that takes only 0.0054mm2 active area. A high-resolution in-situ period jitter measurement block is also incorporated in this design. Finally, a time based digital low dropout (DLDO) regulator architecture is proposed for fine grain power delivery over a wide load current dynamic range and input/output voltage in order to facilitate dynamic voltage and frequency scaling (DVFS). High- resolution beat frequency detector dynamically adjusts the loop sampling frequency for ripple and settling time reduction due to load transients. A fixed steady-state voltage offset provides inherent active voltage positioning (AVP) for ripple reduction. Circuit simulations in a 65nm technology show more than 90% current efficiency for 100X load current variation, while it can operate for an input voltage range of 0.6V – 1.2V.
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    Digital Intensive Transceivers for High-Speed Serial Links
    (2019-11) Chiu, Po-Wei
    Digital intensive circuit is gaining popularity to mixed-signal circuit design as they are friendly to technology scaling. The simple inverter-based implementation is easy to design in the new process while immune to process-voltage-temperature (PVT) variation. The growing complexity equalization technique can benefit from the robustness design to enhance the link performance. Also, as the data rate increases, accurately measurement is more challenge since there is no time-domain calibration for bit error rate (BER). The issue mentioned above motivates the in-situ measurement circuit, which enables simple testing setup and obviates the uncertainty. Three digital intensive high speed serial link transceiver for various kinds of application is proposed in this thesis along with in-situ measurements circuit for BER and channel loss testing. First, a digital-intensive on-chip serial link achieving a 10 Gb/s data rate over a 10mm interconnect was demonstrated in a 65nm GP process. A 3-tap half-rate feed forward equalizer (FFE) was implemented for signal pre-emphasis in the transmitted block. On the receiver side, a 2-tap half-rate time-based decision feedback equalizer (TB-DFE) was employed to cancel out inter-symbol-interference (ISI) noise. A 2^15-1 pseudo random binary sequence (PRBS) generator and an in-situ bit error rate (BER) monitor were designed for bit stream generation and convenient eye-diagram measurements. The measured energy-efficiency of the transmitter and receiver was 31.9 and 45.3 fJ/b/mm, respectively, for a data rate of 10 Gb/s. A BER less than 1E-12 was verified for an eye width of 0.43 Unit Interval (UI). In second work, we present an 8 Gb/s time-to-digital converter (TDC) based receiver with a time-based front-end in 65nm CMOS specifically designed for in-package serial link applications. The proposed receiver converts the channel signal to a corresponding time delay, which is amplified by a novel delay line based time amplifier. Next, a time-to-digital converter generates a 4 bit code which is used for digital equalization. The proposed design is digital intensive and hence highly resilient to voltage headroom and/or PVT issues. A bathtub curve and time-domain eye-diagram were measured by an in-situ BER monitor circuit. An energy-efficiency of 2.1 pJ/b was achieved at 8 Gb/s for a 7 mm link. The receiver area is 240×120μm2. Last, a single-ended digital-intensive four-level pulse amplitude (PAM-4) transceiver with a 2-tap time-based decision feedback equalization (TB-DFE) and an in-situ channel loss monitor has been demonstrated in 65nm CMOS process for high speed memory interface. A proposed differential voltage-to-time converter (DVTC) increases the linearity and dynamic range by 67% compared to prior art. The four-level signal comparison and decision feedback equalization (DFE) operation are performed entirely in the time domain using programmable delays and a phase detector (PD). The in-situ channel loss monitor was proposed to measure the channel loss in the time domain instead of measuring the S-parameter. By using the on-chip BER monitor, the proposed transceiver can achieve BER less than 1E-12 while energy-efficiency is 0.97pJ/b for a 32Gb/s data rate. The chip area includes the transmitter and receiver is 0.009mm2.