Digital Intensive Transceivers for High-Speed Serial Links
2019-11
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Digital Intensive Transceivers for High-Speed Serial Links
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2019-11
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Digital intensive circuit is gaining popularity to mixed-signal circuit design as they are friendly to technology scaling. The simple inverter-based implementation is easy to design in the new process while immune to process-voltage-temperature (PVT) variation. The growing complexity equalization technique can benefit from the robustness design to enhance the link performance. Also, as the data rate increases, accurately measurement is more challenge since there is no time-domain calibration for bit error rate (BER). The issue mentioned above motivates the in-situ measurement circuit, which enables simple testing setup and obviates the uncertainty. Three digital intensive high speed serial link transceiver for various kinds of application is proposed in this thesis along with in-situ measurements circuit for BER and channel loss testing. First, a digital-intensive on-chip serial link achieving a 10 Gb/s data rate over a 10mm interconnect was demonstrated in a 65nm GP process. A 3-tap half-rate feed forward equalizer (FFE) was implemented for signal pre-emphasis in the transmitted block. On the receiver side, a 2-tap half-rate time-based decision feedback equalizer (TB-DFE) was employed to cancel out inter-symbol-interference (ISI) noise. A 2^15-1 pseudo random binary sequence (PRBS) generator and an in-situ bit error rate (BER) monitor were designed for bit stream generation and convenient eye-diagram measurements. The measured energy-efficiency of the transmitter and receiver was 31.9 and 45.3 fJ/b/mm, respectively, for a data rate of 10 Gb/s. A BER less than 1E-12 was verified for an eye width of 0.43 Unit Interval (UI). In second work, we present an 8 Gb/s time-to-digital converter (TDC) based receiver with a time-based front-end in 65nm CMOS specifically designed for in-package serial link applications. The proposed receiver converts the channel signal to a corresponding time delay, which is amplified by a novel delay line based time amplifier. Next, a time-to-digital converter generates a 4 bit code which is used for digital equalization. The proposed design is digital intensive and hence highly resilient to voltage headroom and/or PVT issues. A bathtub curve and time-domain eye-diagram were measured by an in-situ BER monitor circuit. An energy-efficiency of 2.1 pJ/b was achieved at 8 Gb/s for a 7 mm link. The receiver area is 240×120μm2. Last, a single-ended digital-intensive four-level pulse amplitude (PAM-4) transceiver with a 2-tap time-based decision feedback equalization (TB-DFE) and an in-situ channel loss monitor has been demonstrated in 65nm CMOS process for high speed memory interface. A proposed differential voltage-to-time converter (DVTC) increases the linearity and dynamic range by 67% compared to prior art. The four-level signal comparison and decision feedback equalization (DFE) operation are performed entirely in the time domain using programmable delays and a phase detector (PD). The in-situ channel loss monitor was proposed to measure the channel loss in the time domain instead of measuring the S-parameter. By using the on-chip BER monitor, the proposed transceiver can achieve BER less than 1E-12 while energy-efficiency is 0.97pJ/b for a 32Gb/s data rate. The chip area includes the transmitter and receiver is 0.009mm2.
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University of Minnesota Ph.D. dissertation. 2019. Major: Electrical Engineering. Advisor: Chris Kim. 1 computer file (PDF); 103 pages.
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Chiu, Po-Wei. (2019). Digital Intensive Transceivers for High-Speed Serial Links. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/226422.
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