Browsing by Subject "CAD"

Now showing 1 - 3 of 3
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    CAD algorithms dealing with process and temperature effects in digital integrated circuits.
    (2010-01) Mogal, Hushrav
    The aggressive scaling trend of the semiconductor industry to improve integrated circuit performance manifests itself as process, voltage and temperature (PVT) variations which can negatively impact design yield. The aim of this work is to deal with process (P) and temperature (T) effects and to develop software CAD analysis and optimization tools to mitigate their effects on digital integrated circuit performance. In the first part of this thesis, we aim to develop an algorithm to compute the criticality of gates in a circuit with underlying process variations. The timing criticality of a gate indicates its impact on the overall timing performance of a circuit. We propose to use graph-based techniques to linearly traverse the timing graph of a digital circuit to obtain its criticality information. Such information can be useful to a designer or optimization tool in making decisions regarding gate sizing to improve the circuit performance. Our methodology must not only improve the speed of computation but also the accuracy with which we obtain the criticality values of gates in the circuit. In the second part of this thesis, we propose to deal with temperature effects in the presence of increased scaling of devices. The sub-threshold leakage power of a digital chip, which is the wasted power in a digital circuit without doing any useful work, is exponentially dependent on the operating temperature of the chip. We propose to use techniques to exploit this dependence to reduce the sub-threshold leakage power. By rearranging the physical placement we can affect the temperature distribution of various blocks on a digital chip, thereby also affecting the total sub-threshold leakage power. We aim to develop a physical floorplanning tool to alleviate the temperature and sub-threshold leakage power by taking into account their interdependence. This work proposes to use task migration (TM) as a methodology to deal with increasing sub-threshold leakage power in future technology nodes. The main idea is to replicate certain high-power blocks in the design, and migrate tasks at regular intervals from one part of the chip to another, thereby reducing the power density and temperature of the design. We aim to develop a CAD optimization framework using floorplanning to read in a circuit description and produce a physical floorplan layout of the TM-aware design. This involves the selection of the design blocks to replicate, followed by the judicious placement of the blocks and finally the selection of an appropriate migration interval taking into account its negative impact on circuit performance. The traditional semiconductor process technology consists of a single layer of silicon on which various devices like transistors and diodes are fabricated along with several layers of metal. Besides the problems outlined above, increasing device density is forcing larger die footprints. As a result, designers are facing increased congestion of routing wires, limiting the amount of performance benefit with scaling. Three-dimensional or vertical integration technology offers a promising alternative, in which multiple layers of silicon with their associated metal layers are stacked on top of each other. Field-programmable devices are particularly suited to such a technology due to the regular layout of logic and routing elements on the die. As the final part of this thesis, we examine the benefits of vertical integration applied to field programmable logic devices.
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    Is CT Angiography Right for You?
    (2009-05-06) Meyers, Jason
    Given the high sensitivity and negative predictive value of 64-slice CT angiography, a negative result can be used to effectively rule out CAD in the intermediate risk patient, while a positive result can identify those who need to proceed to traditional angiography.
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    Overcoming Physical Design challenges in nanometer-scale integrated circuits
    (2013-02) Wei, Yaoguang
    Through aggressive technology scaling over the past five decades, integrated circuit design has entered the nanometer-scale era. While scaling enables the design of more powerful chips, circuit designers must face numerous challenges that accompany these miniscule feature sizes. Many of these issues are expressed in the step of physical design, an important back-end stage in the integrated circuit design flow. First, the routability of a design becomes an increasingly important and difficult problem, and must be addressed across the entire physical synthesis tool stack. This in turn requires effective routability evaluation methods to be used in the early stages for congestion mitigation. Second, wire delays do not scale down well with process technology, and have exceeded the gate delay in importance, becoming the dominating factor that determines the circuit delay. Wire delays can be reduced by inserting large numbers of buffers, but these can significantly increase the chip area, cost, and power, so that improved methods that control these costs are essential. Third, with shrinking feature sizes, the impact of process variations has become more serious than before. Several important process variation effects show strong dependencies on the underlying patterns on the die, and these challenges can be addressed effectively through appropriate physical design. This thesis presents solutions to these challenges. To achieve effective routability evaluation, we first analyze the problems associated with mainstream global-routing-based congestion analysis tools. Two major deficiencies of existing approaches are: (i) they do not adequately model local routing resources, which can cause incorrect routability predictions that are only detected late, during detailed routing, (ii) the metrics used to represent congestion may yield numbers that do not provide sufficient intuition to the designer; moreover, they may often fail to predict the routability accurately. We propose solutions for both problems. First, we develop an efficient, accurate and scalable local routing resource model. Experiments demonstrate that our model improves the accuracy of a congestion analyzer and enables designers to use a coarser grid to speed up congestion analysis and achieve similar accuracy as the baseline case. Second, we develop a new metric that represents the congestion map for the chip with high fidelity. Experiments show that compared with conventional metrics, the new metric can predict the routability more accurately and can drive a placer to obtain a design that has better routability characteristics. To reduce the buffer usage, we make full use of the timing benefits brought by the thick metal layers. In advanced technologies, a larger number of metal layers with thick cross-sections are available for routing. These metal layers have much smaller wire delays than thinner layers, and assigning nets to these layers can improve timing and save buffer usage. However, existing algorithms have various limitations in using thick metal layers. In this work, we propose a novel algorithm to address the issue. Our algorithm tries to assign as many nets as possible to thick metal layers to maximize the timing benefits while simultaneously using heuristics to control the congestion at a manageable level. We also present a new physical synthesis flow that adds our algorithm as a new component at an early stage of an existing industrial design flow. Experimental results demonstrate the effectiveness of our algorithm and flow on a set of industrial designs. To overcome the challenges from process variations, this thesis presents physical design solutions to two important types of variations induced in the processes of oxide chemical mechanical polishing (CMP) and rapid thermal annealing (RTA). First, since the oxide CMP variation highly depends on the metal pattern density, a common practice to reduce CMP variation is to insert dummy fills. However, dummy fills have side effects on design performance or complexity and should be minimized. Therefore, we propose a novel global routing algorithm directly aiming to minimize the amount of dummy fills necessary to satisfy the requirements for CMP. Since it is not computationally efficient to directly minimize the amount of dummy fills in the routing process, we develop a surrogate optimization objective through theoretical analyses and experiments. Then effective cost functions are elaborated and applied in the routing process to optimize the surrogate metric. Our strategy and algorithm is validated by the experiments on a standard set of benchmark circuits. Second, since RTA variation strongly depends on the density of the STI regions, to minimize RTA variation, this thesis proposes a two-step approach to maximize the uniformity of the STI density throughout the layout. We introduce a concept of effective STI density and propose an efficient incremental method to compute it for the whole circuit. Furthermore, we enhance a conventional floorplanner to handle the new objective of minimizing the variations in effective STI density, using a two-stage simulated annealing heuristic. As the second step of our efforts, we insert dummy polysilicon fills to further minimize the variation in effective STI density. Experimental results demonstrate that our methods can significantly reduce the RTA variations.