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Browsing by Author "Shragowitz, Eugene"

Now showing 1 - 6 of 6
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    Combining Hierarchical Filtering, Fuzzy Logic, and Simulation with Software Agents for IP (Intellectual Property) Selection in Electronic Design
    (2000-02-04) Liu, Jian; Shragowitz, Eugene; Tsai, Wei-Tek
    One of the central issues in electronic design is reuse of existing design solutions (IPs). This paper describes an Internet-based distributed system of software agents, performing dialogue with the users, search of IPs over Internet, filtering and evaluation of IPs based on fuzzy logic and vendor site simulation environment. Application of this system allows the potential user to speed up the search process and improve the quality of selected solutions.
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    Functional Verification in IP Selection by Black-box Logic Simulation
    (2001-04-09) Liu, Jian; Shragowitz, Eugene
    Reuse of IPs is an important feature of contemporary SoC design. To select an IP for reuse, it is desired to verify that the proposed design solution satisfies the specification formulated by the SoC designers prior to the purchase of IPs. Formal verification and simulation are the two major approaches for functional verification. Since the implementation details of IPs are usually not released by suppliers, formal verification is not applicable in such an environment, and simulation is left as a practical alternative. This paper presents a framework for verification of functional equivalence between the model presented by the customer and the model by IP supplier. The methodology is based on the joint simulation of an IP and the user model. In this framework, the IPs are modeled as black boxes, in other words, no knowledge about the internal structure of IPs is assumed. The proposed framework establishes equivalence of design solutions by comparing waveforms at the output ports of respective models. It is not very likely that two independently developed models for the same specification will produce completely identical waveforms at all specified ports for the same testbenches. Causes of differences in waveforms are numerous and may include such factors as different number of clock cycles per operation. Nevertheless, in spite of such differences in some waveforms produced in response to the same stimuli, it is possible that the IP in consideration still could be used as an alternative. Commercial simulation tools have limited capability for comparison of waveforms since they see similarity only if one waveform presents version of another displaced in time. In this project we propose to automate a substantial part of this process. Before comparison, the output signal waveforms are coded into strings. A set of metrics for waveform comparisons is proposed to determine equivalence of waveform strings. Each metric is associated with possible constraints. The waveform strings are deemed as equivalent if the one string can be transformed into the other under the constraints. One important metric is a regular expression based pattern matching. A user can supply the knowledge about acceptable waveform divergence in the form of regular expression, which has been proven effective in describing system behavior such as model interface. The algorithms and correspondent complexity are also described in the paper. This methodology can be applied to a variety of digital designs, therefore it provides a new way to verification models based on black-box logic simulation.
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    Iterative Converging Algorithms for Computing Bounds on Durations of Activities in Pert and Pert-like Models
    (2001-04-06) Shragowitz, Eugene; Youssef, Habib; Lu, Bing
    Since its invention in 1958, Program Evaluation and Review Technique (PERT) has been widely used during the planning, design, and implementation of projects. Pert models the activities of a project as a single source-single sink directed acyclic graph where nodes represent events (end or beginning of activities) and arcs activities. The maximum amount by which an activity can be delayed without delaying the overall project is called the slack. Critical tasks have zero slack whereas all noncritical tasks have positive slacks. Pert is a valuable tool in the management of large projects since it allows to compute the slack of each activity of the project. Such information may be crucial in avoiding cost overruns that would be caused by delays to critical activities and/or excessive delays to noncritical activities. What Pert fails to provide is how one should go about distributing remaining slack on non-critical activities while taking into consideration properties of the activities as well as precedence relationships among them, so as to have reasonable upper bounds on duration of all activities, critical or noncritical. In this paper we propose several algorithms for the distribution of slack on noncritical activities. We show that if one desires to distribute the remaining slack proportionally to the initially assigned activity durations then the problem is in P, and propose an algorithm of linear time complexity. However if one desires to use distribution functions other than the initial durations of activities, then the problem of slack distribution becomes NP-complete. Finding the maximal bounds corresponding to zero-slack solution at the sink requires iterative application of exponential algorithm. For that case we introduce an approximation algorithm of linear time complexity on each iteration. The algorithm iteratively increases bounds on durations of activities and converges to the zero-slack solution on all paths from the source node to the sink node in the Pert-like graph. The algorithms described in this paper were successfully applied to solving timing bounds problems in VLSI design.
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    New Bound-Based Net Criticality Metrics for Timing-Driven Physical Design
    (2001-06-11) Shragowitz, Eugene; Chang, Hongliang; Liu, Jian; Youssef, Habib; Lu, Bing; Sutanthavibul, Supachai
    A target of this work is improving timing characteristics of layout and optimizing design flow by reducing the number of iterations required for a timing closure. This goal is achieved by introducing new criticality metrics that could be computed prior to placement and routing respectively and converted to weights of nets supplied to a placer and to a router. These new metrics are defined as a ratio of a net parameter to a net delay bound. The net delay bounds used in this paper are computed by the Iterative Minimax algorithm of Youssef et. al. (see references in the text). This algorithm has the lowest time complexity (linear) among all algorithms proposed for the computation of delay bounds and corresponds well with therequirements of layout tools. In this paper, a contribution is also made to the bound on the delays theory by proving that there is an infinite number of solutions for the zero-slack distribution problem. It is also explained why net bounds derived from a linear programming formulation could be difficult to implement on the placement step of layout. Part II: This report proposes new net criticality metrics and one pass design flow methodology for timing-driven physical design. The proposed net criticality metrics employ net parameters and bounds on net delays derived by the Minimax algorithm. The criticality metrics were mapped to weightsin the Cadence Silicon Ensemble DSM Automatic Layout System and produced in one-pass layouts with the clock cycle approximately 29% faster in average than without criticality evaluation. Criticality metrics are independent of layout tools producing actual placement and routing.Criticality calculation could be integrated with any layout system that allows weights for individual nets on the placement and routing steps. In the section on Criticality Metrics, it is proven that the net parameters strongly correlated to net delay could be used in formulas for criticality metrics. They provide the same relative ranking of nets with respect to the net criticality metrics as the projected net delays. On this ground, the new criticality metrics based on net parameters and delay bounds are introduced for placement and routing stages of layout respectively. These criticality metrics computed for each net in the design are sorted in the descending order to produce relative ranking of nets with respect to the net criticality. From the ordered list of criticality metrics weights are derived by layout systems. In the experimental part of this work, the proposed design flow and the criticality metrics were integrated with the Cadence SE (Silicon Ensemble) DSM Automatic Layout System (version 5.2.158). The SE system was allowed to place and route a set of designs in several modes with and without weights produced from the proposed new criticality metrics. With weights provided by the new criticality metrics, the SE system achieved reduction in the clock cycle by 27% in average for the set of tests in one iteration of layout. It also significantly outperformed attempts to reduce a clock rate by repeated iterations of layout and by using timing-driven version of the SE Layout System. A conclusion is that new metrics could be useful for all layout tools that allow weights to be assigned to nets.
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    Timing Domain Algorithm for Nonlinear Optimization Problems in Interconnect Design
    (2000-05-10) Raha, Soumyendu; Shragowitz, Eugene
    The necessity for computing robustly accurate sensitivities repeatedly for direct solution of nonlinear optimization problems and possibility of dealing with nonlinear circuit elements motivate a revisit of time domain methods. This paper illustrates the possibility of developing an efficient sysnthesis/analytical tool for high-speed interconnect networks by (a) employing a stable and fast time-domain numerical integration scheme to simulate the continuous approximation of the wave equation for transmission lines and to generate highly accurate sensitivities, and (b) using the integrator in multiple-shooting type signal-integrity-constrained non-linear optimizer to obtain values of the design parameters.
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    Transaction-based Waveform Analysis for Functional Verification in IP Selection
    (2001-12-13) Liu, Jian; Shragowitz, Eugene
    Functional verification is an important aspect of IP selection. Formal verification and logic simulation are two traditional approaches for this problem. Both technqiues have substantial limiations. A methoddescribed in our work combines these two basic approach to achieve effective verification. A formal regular expression technique is merged with the simulation to provide meaningful transaction level verification of IP suitability. Implementation is illustrated by examples.