Functional Verification in IP Selection by Black-box Logic Simulation

Abstract

Reuse of IPs is an important feature of contemporary SoC design. To select an IP for reuse, it is desired to verify that the proposed design solution satisfies the specification formulated by the SoC designers prior to the purchase of IPs. Formal verification and simulation are the two major approaches for functional verification. Since the implementation details of IPs are usually not released by suppliers, formal verification is not applicable in such an environment, and simulation is left as a practical alternative.

This paper presents a framework for verification of functional equivalence between the model presented by the customer and the model by IP supplier. The methodology is based on the joint simulation of an IP and the user model. In this framework, the IPs are modeled as black boxes, in other words, no knowledge about the internal structure of IPs is assumed. The proposed framework establishes equivalence of design solutions by comparing waveforms at the output ports of respective models. It is not very likely that two independently developed models for the same specification will produce completely identical waveforms at all specified ports for the same testbenches. Causes of differences in waveforms are numerous and may include such factors as different number of clock cycles per operation.

Nevertheless, in spite of such differences in some waveforms produced in response to the same stimuli, it is possible that the IP in consideration still could be used as an alternative. Commercial simulation tools have limited capability for comparison of waveforms since they see similarity only if one waveform presents version of another displaced in time. In this project we propose to automate a substantial part of this process. Before comparison, the output signal waveforms are coded into strings. A set of metrics for waveform comparisons is proposed to determine equivalence of waveform strings. Each metric is associated with possible constraints. The waveform strings are deemed as equivalent if the one string can be transformed into the other under the constraints. One important metric is a regular expression based pattern matching. A user can supply the knowledge about acceptable waveform divergence in the form of regular expression, which has been proven effective in describing system behavior such as model interface. The algorithms and correspondent complexity are also described in the paper. This methodology can be applied to a variety of digital designs, therefore it provides a new way to verification models based on black-box logic simulation.