Browsing by Author "Li, Zhiyuan"
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Item Design & Implementation of a Framework for Integrating Front-End & Back-End Compilers(1999-04-20) Yew, Pen-Chung; Li, Zhiyuan; Song, Yonghong; Tsai, Jenn-Yuan; Zheng, BixiaWe propose a new universal High-Level Information (HLI) format to effectively integrate front-end and back-end compilers by passing front-end information to the back-end compiler. Importing this information into an existing back-end leverages the state-of-the-art analysis and transformation capabilities of existing front-end compilers to allow the back-end greater optimization potential than it has when relying on only locally-extracted information. A version of the HLI has been implemented in the SUIF parallelizing compiler and the GCC back-end compiler. Experimental results with the SPEC benchmarks show that HLI can provide GCC with substantially more accurate data dependence information than it can obtain on its own. Our results show that the number of dependence edges in GCC can be reduced substantially for the benchmark programs studied, which provides greater flexibility to GCC's code scheduling pass, common subexpression elimination pass, loop invariant code removal pass and register local allocation pass. Even with GCC's optimizations limited to basic blocks, the use of HLI produces moderate speedups compared to usng only GCC's dependence tests when the optimized programs are executed on a MIPS R10000 processor.Item Reducing Cache Misses for CC-NUMA by Careful Page-mapping(1997) Huang, Jian; Li, ZhiyuanCareful page mapping has been shown in the past to be effective for reducing cache conflicts on both uniprocessor and Uniform Memory Access (UMA) multiprocessors. We extend previous page-mapping schemes to Cache-Coherent Non-Uniform Memory Access (CG-NUMA) multiprocessors. These extensions maintain the program's data-task affinity, which is important to CG-NUMA, while reducing cache set conflicts by carefully selecting the page frames. Using an execution-driven simulator that simulates a CC-NUMA machine with a 2-MB secondary cache and a 16-KB primary cache on each of the 16 four-issue super-scalar processors, we find that a simplistic application of page-coloring performs worse than bin-hopping by 10-45%, while by hashing the page color with part of the MID bits, page-coloring can perform closely to bin-hopping.Item Superthreading: Integrating Compilation Technology and Processor Architecture for Cost-Effective Concurrent Multithreading(1997) Tsai, Jenn-Yuan; Jiang, Zhenzhen; Li, Zhiyuan; Lilja, David; Wang, Xin; Yew, Pen-Chung; Zheng, Bixia; Glamm, RobertAs the number of transistors that can be integrated on a single chip continues to grow, it is important for computer architects to think beyond the traditional approaches of deeper pipelines and wider instruction issue units for improving performance. This single-threaded execution model limits these approaches to exploiting only the relatively small amount of instruction-level parallelism available in application programs. While integrating an entire multiprocessor onto a single chip is feasible, this architecture is limited to exploiting only relatively coarse-grained heavy-weight parallelism. We propose the superthreaded architecture as an excellent alternative for utilizing the large number of transistors that will become available on a single high-density chip. As a hybrid of a wideissue superscalar processor and a multiprocessor-on-a-chip, this new concurrent multithreading architecture can leverage the best of existing and future parallel hardware and software technologies. By incorporating speculation for control dependences and run-time checking of data dependences, the superthreaded architecture can exploit the multiple granularities of parallelism available in general-purpose application programs to reduce the execution time of a single program.