Browsing by Author "Lee, Gyungho"
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Item A Non-blocking Directory Protocol for Large-Scale Multiprocessors(1999-04-08) Kong, Jinseok; Yew, Pen-Chung; Lee, GyunghoThis paper presents a non-blocking directory-based cache coherence protocol to improve the performance of large-scale distributed shared-memory multiprocessors. In the proposed non-blocking directory protocol, all subsequent request can proceed without being blocked at the directory. The critical path of a data access and the amount of network transactions needed to complete a memory request (including the transactions needed to maintain coherence) are also reduced. To support the non-blocking directory protocol, the history of data accesses is maintained with a small history table at the directory. Using detailed simulations,we evaluate the performance of the protocol compared with other blocking directory protocols.Item Access Region Locality for High-Bandwidth Processor Memory System Design(1999-02-15) Cho, Sangyeun; Yew, Pen-Chung; Lee, GyunghoThis paper explores an important behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data loacality that focuses on individual memory locations and how accesses to the locations are inter-related, the access region locality concerns with each static memory instruction and its range of access locations at run time. We consider program's data, heap, and stack regions in this paper. Our experimental study using a set of SPEC95 benchmark programs show that most memory reference instructions access a single region at run time. Also shown is that it is possible to predict the access region of a memory instruction accurately at run time by scrutinizing the addressing mode of the instruction and the past access region history of it. An important implication of the access region locality is that two memory accesses to different regions are data independent. Utilizing this property, we evaluate a novel processor memory system and pipeline design which can provide high data cache bandwidth without increasing the critical path of the processor, by decoupling the memory instructions that access program's stack at an early pepeline stage. Experimental results indicate that the proposed technique achieves comparable or better performance than a conventional memory design with a heavily multi-ported data cache that can lead to much higher hardware complexity.Item Minimizing the Directory Size for Large-scale DSM Multiprocessors(1999-01-09) Kong, Jinseok; Yew, Pen-Chung; Lee, GyunghoDirectory-based cache coherence schemes are commonly used in large-scale distributed shared-memory (DSM) multiprocessors, but most of them rely on heuristics to avoid large hardware requirements. We proposed to use physical address mapping on the memory modules to significantly reduce the directory size needed. This approach allows the size of directory to grow as O (cn log2n) as in optimal pointer-based directory schemes [10], where n is the number of nodes in the system and c is the number of cache lines in each cache memory. Our simulations show that the proposed scheme can achieve a performance equivalent to the heuristic pointer-based directory schemes, but with a smaller directory size and a simpler pointer management scheme.