Access Region Locality for High-Bandwidth Processor Memory System Design

Abstract

This paper explores an important behavior of memory access instructions, called access region locality. Unlike the traditional temporal and spatial data loacality that focuses on individual memory locations and how accesses to the locations are inter-related, the access region locality concerns with each static memory instruction and its range of access locations at run time. We consider program's data, heap, and stack regions in this paper. Our experimental study using a set of SPEC95 benchmark programs show that most memory reference instructions access a single region at run time. Also shown is that it is possible to predict the access region of a memory instruction accurately at run time by scrutinizing the addressing mode of the instruction and the past access region history of it. An important implication of the access region locality is that two memory accesses to different regions are data independent. Utilizing this property, we evaluate a novel processor memory system and pipeline design which can provide high data cache bandwidth without increasing the critical path of the processor, by decoupling the memory instructions that access program's stack at an early pepeline stage. Experimental results indicate that the proposed technique achieves comparable or better performance than a conventional memory design with a heavily multi-ported data cache that can lead to much higher hardware complexity.