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Browsing by Author "Jiao, Dong"

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    Circuit modeling and design techniques for efficient power delivery under resonant supply noise
    (2011-07) Jiao, Dong
    Power supply noise has become one of the main performance limiting factors in sub-1V technologies. Resonant supply noise caused by the package/bonding inductance and on-die capacitance has been reported as the dominant supply noise component in high performance microprocessors. Recently, adaptive clocking schemes have been proposed to mitigate the impact of resonant noise. Here, the clock period is intentionally modulated by the resonant noise when it is generated in PLL or propagates through the clock distribution. As a result, the increased clock period partially compensates for the increased datapath delay which is also modulated by the same resonant noise and this is called clock data compensation effect, or beneficial jitter effect. This thesis presents a comprehensive study of this clock data compensation effect including an analysis of its dependency on various design parameters. A mathematical framework, including both an analytical model and a numerical model, is also proposed to accurately describe this timing compensation effect. To achieve optimal timing compensation, a certain amount of phase shift and proper adjustment of the clock period's sensitivity to supply noise are required. Here we also propose phase-shifted clock distribution designs and an adaptive phase-shifting PLL design to enhance the beneficial clock data compensation effect. Compared with conventional approaches, the proposed phase-shifted clock distribution designs save 85% of the clock buffer area while achieving a similar amount of improvement in the maximum operating frequency (Fmax) for typical pipeline circuits. In the proposed adaptive phase-shifting PLL, both the phase shift and the supply noise sensitivity of the clock can be digitally programmed and adjusted so that the optimal compensation can always be achieved under different conditions. Two test chips were fabricated in a 65nm CMOS process for concept verification. Measurement results demonstrate that the proposed phase-shifted clock distribution designs can provide an 8-27% performance improvement in Fmax for typical resonant noise frequencies from 100MHz to 300MHz and the proposed phase-shifting PLL can provide 3-7% improvement in Fmax under various operating conditions.