Reduced-complexity VLSI architectures for binary and nonbinary LDPC Codes.

Abstract

This thesis proposes efficient algorithm and architecture aspects for binary and nonbinary low- density parity-check (LDPC) codes by developing optimal quantization approaches, decoding algorithms, decoding schedules and switch networks based on the characteristics of specific codes. To provide a quantitative comparison with previous work, including design performance and cost, we implement and analyze our architectures using a Field Programmable Gate Array (FPGA) platform. The decoding of LDPC codes uses soft information, so it is important to analyze the error correcting performance with fixed-point computations. An adaptive quantization scheme to select suitable input values for the min-sum based decoding algorithm is given. Our simulation results show that it gives good error correcting performance compared with the conventional method. A reduced-complexity LDPC layered decoding architecture is proposed using an offset permutation scheme in the switch networks. Then, a switch network for the code rates defined in the IEEE 802.15.3c standard is optimized by reducing the number of control bits and eliminating unnecessary switch elements. We implement a 672-bit, rate-1/2 irregular LDPC code on a Xilinx Virtex-4 FPGA device and this design achieves an information throughput of 822 Mb/s at a clock speed of 335 MHz a maximum of 8 iterations. We propose an improved nonbinary decoding algorithm with a threshold factor to increase the performance of LDPC decoders. Implementing nonlinear functions as small look-up table leads us consider the dynamic range of the nonlinear functions in order to take more precisely into account the effect of finite precision computation. Finally, an efficient VLSI architecture for a nonbinary LDPC decoder will be presented.