Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors
1997
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Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors
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1997
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Abstract
In this paper, we study a hardware-supported, compiler-directed (HSCD) cache coherence
scheme, which can be implemented on a large-scale multiprocessor using off-the-shelf microprocessors,
such as the Cray T3D. The scheme can be adapted to various cache organizations,
including multi-word cache lines and byte-addressable architectures. Several system related
issues, including critical sections, inter-thread communication, and task migration have also
been addressed. The cost of the required hardware support is minimal and proportional to the
cache size. The necessary compiler algorithms, including intra- and interprocedural array data
flow analysis, have been implemented on the Polaris parallelizing compiler [33].
From our simulation study using the Perfect Club benchmarks [5], we found that in spite
of the conservative analysis made by the compiler, the performance of the proposed HSCD
scheme can be comparable to that of a full-map hardware directory scheme. Given its comparable
performance and reduced hardware cost, the proposed scheme can be a viable alternative
for large-scale multiprocessors such as the Cray T3D, which rely on users to maintain data
coherence.
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Choi, Lynn; Yew, Pen-Chung. (1997). Hardware and Compiler-Directed Cache Coherence in Large-Scale Multiprocessors. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/215312.
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