Memory Design for Centimeter-Scale Organic and Nanometer-Scale Silicon Technologies

Abstract

Low power memory is always desired due to its significance in many large-scale applications. It is important to emerging technologies such as organic electronics, since it is an indispensible component to extend the technology towards larger application scope with complicated functionalities. It is also a hot topic in the mature silicon technology because the device scaling makes memory designs challenging with increasing leakage currents and process variations. Organic electronics deals with conductive polymers and plastics, and is capable of realizing large area flexible applications, which cannot be fulfilled by modern silicon technology. Conventional organic devices require a high operation voltage due to its low carrier mobility. Ion-gel gated OTFTs (gel-OTFTs), however, deliver unusually high gate capacitance through an electrolyte-gated structure, and therefore offer sufficient drive currents under a low voltage. Being an emerging technology, few attempts have been made on organic memory designs. In this dissertation, we first propose an improved design-fabrication-testing flow to significantly facilitate the entire process, which boosts the design efficiency and fabrication yield and thus enables the implementation of complex circuits such as memory array. An organic process design kit (OPDK) with various modeling approaches allows designers to easily design organic circuits in a similar way as that in silicon technology. Various circuit components including logic gates, ring oscillators and a D-flipflop were demonstrated and a general purpose organic dynamic memory cell was proposed for the first time. The cell, known as a DRAM gain cell, achieves a sub-10nW-per-cell refresh power with a retention time of over 1 minute, which is 5 orders of magnitude longer than that in silicon designs. The same DRAM gain cell architecture is also found potential as embedded memory in the modern silicon technology, where the prevailing 6T SRAM is suffering from leakage power and poor low voltage margin when devices keep scaling down. In this dissertation we report the first variation-aware performance analysis on the silicon gain cell and reveal that conventional corner simulations are no longer valid in capturing worst cases of gain cells. Insights can be obtained through the various analysis approaches described in the dissertation to benefit future memory design strategy and device optimization. With innovations in cell structure and peripheral circuitry, the silicon gain cell performance can be further enhanced to compete with the mainstream 6T SRAM. In this dissertation, we for the first time experimentally demonstrate a gain cell design with write-back-free read operations, utilizing its non-destructive read nature to improve the read speed into GHz regime without sacrificing retention time. Various circuit techniques including a local-sense-amplifier architecture are proposed to eliminate the need of a complex current-sensing scheme, and a dual-row-access mode is proposed for further power saving in half-utilization scenarios. The test chip in a 65nm low power process achieves a 23.9% power saving compared to a 6T SRAM at 0.6V retention voltage and an additional 27.8% power saving during cases when only half array is needed.