Variation-aware and aging-aware design tools and techniques for nanometer-scale integrated circuits

Abstract

Shrinking feature sizes in CMOS-based technology beyond the 45nm regime have given rise to increased levels of variation in digital circuits and architectures due to process, temperature, and aging effects. The fabrication process induces variations in the process parameters, causing differing levels of perturbation in the circuit delay in each manufactured part at the postsilicon stage. Moreover, after manufacturing, during the normal operation of a chip, new variations are injected due to various aging mechanisms, particularly Bias Temperature Instability (BTI). These effects cause long-term degradations in transistor performance, resulting in temporal delay degradations at the circuit level. The mechanism of BTI is exacerbated as transistor sizes reduce, and poses a growing threat to circuit reliability. All of these effects poses significant challenges at the presilicon design stage, which must ensure correct and reliable performance of a chip throughout its lifetime. Hence, techniques to mitigate the effects of spatial and temporal variations have become a vital part of the design flow for digital circuits and architectures. In this thesis, we develop robust techniques, in the form of design tools and techniques that operate at the circuit and architectural levels, which can be used to analyze, compensate and mitigate various sources of variation, including process and temperature variations and BTI-induced aging. One significant problem is related to the issue of performing presilicon timing analysis. State-of-the-art timing tools are built around the use of current source models (CSMs), which have proven to be fast and accurate in enabling the analysis of large circuits. As circuits become increasingly exposed to process and temperature variations, there is a strong need to augment these models to account for thermal effects and for the impact of adaptive body biasing, a compensatory technique that is used to overcome on-chip variations. However, a straightforward extension of CSMs to incorporate timing analysis at multiple body biases and temperatures results in unreasonably large characterization tables for each cell. The first contribution of this thesis is to propose a new approach to compactly capture body bias and temperature effects within a mainstream CSM framework. Our approach features a table reduction method for compaction of tables and a fast and novel waveform sensitivity method for timing evaluation under any body bias and temperature condition. The next part of the thesis addresses the problem of designing a new form of logic circuit, known as a variable latency unit. The basic idea, proposed in prior research, is an alternative to the conventional one-cycle implementation of circuits. Variable latency units (VLUs) allow a circuit to complete its operation in either one or multiple (typically, two) clock cycles, depending on the input provided to the circuit. This is facilitated through the use of hold logic, which holds the clock for an extra cycle when certain input patterns are applied. Our second contribution develops VLU-based BTI-aware designs, with a novel scheme for multioutput hold logic implementation for VLUs. A key observation is the identification and exploitation of specific supersetting patterns in the two-dimensional space of frequency and aging of the circuit. The multioutput hold logic scheme is used in conjunction with an adaptive body bias framework to achieve high performance. VLUs may experience functional incorrectness due to process variations. In our third contribution, we develop an efficient, combined presilicon-postsilicon statistical technique for variation aware VLU design. We develop a set of hold logics that ensure functional correctness of the circuit across all manufactured chips. This is achieved by exploiting spatial correlations to cluster such paths in the circuit, that get affected by process variations in very similar ways. Since such clusters are quite few in number, the corresponding set of hold logics is also small. Our final contribution presents a novel scheme for saving architectural power by mitigating BTI in digital circuits, inspired by the notion of human circadian rhythms. The method works in two alternating phases. In the first, the compute phase, the circuit is "awake" and active, operating briskly at a greater-than-nominal supply voltage, which causes tasks to complete more quickly. In the second, the idle phase, the circuit is power-gated and "put to sleep," enabling BTI recovery. Since the wakeful stage works at an elevated supply voltage, it results in greater aging than operation at the nominal supply voltage, but the sleep state involves a recovery that more than compensates for this differential. At about the same performance, this approach results in appreciable BTI mitigation.