Array-Based On-Chip Hardware Monitors for Statistically Efficient Integrated Circuit Reliability Characterization

Abstract

The miniaturization of feature sizes with every technology generation in accordance with Moore’s Law coupled with the innovations in the transistor design have resulted in a significant performance improvement over the years. However, this has also introduced additional reliability concerns, such as increased on-chip current densities, self-heating effects, process variations, increased susceptibility to radiation-induced soft errors due to the increased device counts and the like. Accurate assessment of process reliability from multiple perspectives has therefore now become quintessential for every upcoming technology generation. To this end, the efforts in this thesis are focused towards circuit-based techniques aimed at making accurate reliability assessment on-chip feasible, and yet simple, by, 1) reducing the equipment complexity, 2) improving the die-area utilization (or the Devices-Under-Test (DUT) count), 3) improving test-efficiency by providing data from a statistically significant sample size in a limited amount of time, 4) ensuring representativeness to the real-case scenario and 5) making the mode selection and data collection easy using a simplistic digital on-chip control. In this work we have proposed and implemented five such array-based characterization vehicles: The first one is a hardware monitor for studying the aging dynamics of diode-connected MOSFETs, the second is a test-vehicle for characterizing Electromigration (EM) induced resistance degradation on-chip, the third is a fully-digital EM characterization macro wherein monitoring the Bit-Error-Rate (BER) of the interconnect path is proposed as a new metric for capturing the impact of EM induced resistance shifts directly in terms of the interconnect path’s signaling ability, the fourth one features a combination of capabilities borrowed from the previous two EM test-vehicles, the motivation being the translation of a measured resistance change to an accompanying change in the measured BER of an interconnect path and finally, the fifth one is a highly scalable, standard combinational logic oriented Soft-Error-Rate (SER) and Single-Event-Transient (SET) pulsewidth characterization macro. Each of the proposed test-vehicles and measured data obtained thereof have demonstrated a methodology for easy and statistically efficient on-chip reliability characterization in comparison to the conventional industry-standard approaches, while also advancing the current state of the art.