Automated layout of analog arrays in advanced technology nodes

Abstract

Arrays of active and passive devices are widely employed to translate large transistor sizes from a circuit schematic to their layout implementation. For example, capacitive digital-to-analog converters (DACs), which enable signal translation from the digital to the analog realm for audio, video, and communication systems, use passive arrays that are built to mitigate variations among matched devices in analog circuits; power amplifiers (PAs), which are essential for wireless communication, audio systems, and RF applications, use arrays of large transistors to enhance signal strength by amplifying signal power. The design of these arrays can greatly benefit from automation. It is widely accepted that although analog circuits have a small area footprint in mixedsignal systems, their design is predominantly manual, requiring specialized expertise and meticulous precision. These factors create a significant bottleneck in design productivity. Automating the layout and performance evaluation of circuits such as DACs and PAs enhances design accuracy, consistency, and efficiency, reducing development time and costs. This automation enables performance optimization and scalability, allowing the development of reliable, high-quality designs that meet stringent specifications, thus accelerating the development cycle and improving overall product quality, and automating the layout of array structures is a vital task in this context. For capacitive DACs, process variations and the effects of interconnect parasitics can cause significant perturbations in their performance metrics. This thesis develops fast constructive procedures for common-centroid (CC) placement and routing for binary-weighted capacitor arrays of charge-sharing DACs to mitigate these effects. The approach particularly targets FinFET technologies, where wire and via parasitics are significant: in these technology nodes, it is shown that the switching speed of the capacitor array, as measured by the 3dB frequency, can be severely degraded by these parasitics, and develop techniques to place and route the capacitor array, for binary-weighted DAC, to optimize the switching speed. A balance between 3dB frequency and INL/DNL metrics is demonstrated by trading off via counts with dispersion in the capacitive array. The approach delivers high-quality results with low runtimes. The layout area and power consumption of a charge-scaling DAC, which is typically dominated by the capacitor array. For binary-weighted DAC structures, the number of unit capacitors in the array increases exponentially with the number of bits, and minimizing the size of the unit capacitor or the number of unit capacitors is crucial for controlling the layout area. The split DAC is an alternative configuration in which an additional attenuation capacitor is integrated to separate the capacitor arrays handling the LSBs and MSBs within the circuit diagram. While the use of a split DAC, which uses many fewer unit capacitors than the binary-weighted DAC, helps to reduce the DAC layout area, it requires the use of non-integer multiples of a unit capacitance. The CC placement approach for binary-weighted DACs is extended to split DACs to optimize 3dB frequency and linearity metrics. The above approaches choose a user-specified unit capacitor, but the choice of unit capacitor can greatly impact the area and power dissipation of a capacitive array. The next part of the thesis addresses this issue, for both binary-weighted and split DACs, by choosing an optimal unit capacitor value. A smaller unit capacitor results in lower area and power, but can be susceptible to larger amounts of noise and process mismatch, and can also be affected by mismatch in the parasitics of routing wires that connect the capacitors in the array. The latter is particularly significant in FinFET nodes, and noise and mismatch can degrade critical DAC performance metrics unless the unit capacitor is sufficiently large. An analytical method to minimize the unit capacitance values is proposed, for both binary-weighted and split capacitor arrays, while considering factors such as noise sources and parasitic components. This method aims to optimize the nonlinearity metrics of DACs by selecting unit capacitance values for both binary-weighted and split capacitor arrays, taking into account systematic and random variations, wire parasitics, flicker noise, and thermal noise. This approach directly links the choice of unit capacitance to circuit-level performance metrics like linearity and 3dB frequency, providing a comprehensive strategy for charge-scaling DAC design. The final segment of the thesis addresses the design of arrays of active devices, specifically FinFET transistors, with a focus on PAs. In FinFET nodes, high power densities in PA transistors and constrained heat transfer pathways lead to significant device self-heating (SH), degrading PA performance. This study investigates the impact of SH in the large FinFET arrays used in PA circuits and quantifies its impact on performance. To overcome the high computational cost of transistor-level thermal analysis, an encoder-decoder neural network, together with a long short-term memory (LSTM) model, is used for rapid and accurate thermal analysis. This fast analyzer facilitates the exploration of design optimizations that were previously impossible with conventional computationally expensive thermal solvers. The work explores methods for mitigating temperature rise effects in PAs through the insertion of dummy transistors within the array of active FinFET devices and examines the influence of duty cycle and frequency on PA performance.