Development and evaluation of a place and route flow using Virtuoso-GXL layout tool suite.

Abstract

In this work, the automatic placement and routing tools from Cadence Virtuoso(R)-GXL layout tool suite have been used to create a flow to allow automatic placement and routing of small to medium sized blocks using schematic or verilog gate-level netlist as input, for aiding the design of testchips. The flow has also been tried on a larger design and timing results are compared with results from a commercial P&R tool-Cadence Encounter(R) Digital Implementation System.