Design techniques for ultra-low voltage sub-threshold circuits and on-chip reliability monitoring.

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Design techniques for ultra-low voltage sub-threshold circuits and on-chip reliability monitoring.

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Transistor scaling has driven the development of semiconductor industry over the last few decades. However, scaling has also generated numerous challenging problems over technology nodes such as power consumption and circuit variability. Power and circuit variability has continuously increased over technology generations, becoming significant concerns for circuit designers. Various circuit techniques have been developed to address these issues. Recently, ultra-low power or energy systems are becoming more and more popular. These systems include implantable biomedical electronics, wireless sensor nodes, RFID tag, and many portable electronics. For these applications where minimal energy consumption is the primary design constraint, sub-threshold logic circuits are becoming increasingly accepted since they consume roughly an order of magnitude less power, compared with normal strong-inversion operation. The first half of this thesis makes several contributions that facilitate reliable sub-threshold circuit design. First, we present a device-size optimization method for sub-threshold circuits utilizing reverse short-channel effect (RSCE) to achieve high drive current, low device capacitance, less sensitivity to random dopant fluctuations, better sub-threshold swing, and improved energy dissipation. Second, we apply the proposed sizing method to SRAMs and propose several circuit techniques for sub-threshold SRAMs that improve SRAM cell stability, writability, bitline sensing margin, and power reduction. By combining these proposed circuit techniques, we demonstrate two fully functional sub-threshold SRAMs in 130nm process technology. Circuit variability is another big challenging issue in nano-scale technologies. Transistor aging is becoming one of the most pressing sources of circuit variations with each technology node. Transistor aging includes various mechanisms such and hot carrier injection (HCI), bias temperature instability (BTI), and time dependent dielectric breakdown (TDDB). One of the most dominant components among these challenges is NBTI, which is characterized by a positive shift in the absolute value of the PMOS threshold voltage. In the second half of this thesis, we propose a fully-digital on-chip reliability monitor for high resolution frequency degradation measurements of digital circuits. The proposed technique measures the beat frequency of two ring oscillators; one stressed, the other unstressed; to achieve 50X higher delay sensing resolution than prior techniques. We also show ring oscillator based test structures that can separately measure the NBTI and PBTI degradation effects in digital circuits for high-k metal-gate devices. Finally, we present a test macro for fully-automated statistical measurements of SRAM Vmin degradation induced by NBTI. An automated test sequence collects Vmin data for statistical analysis and reduces measurement time. Various test strategies were proposed for Vmin measurements to identify different SRAM fail metrics such as SNM failure and access time failure.


University of Minnesota Ph.D. dissertation. October 2009. Major: Electrical Engineering. Advisor: Chris H. Kim. 1 computer file (PDF); xix, 193 pages.

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Kim, Tae-Hyoung. (2009). Design techniques for ultra-low voltage sub-threshold circuits and on-chip reliability monitoring.. Retrieved from the University Digital Conservancy,

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