Speculative Register Promotion Using Advanced Load Address Table (ALAT)

Abstract

Register promotion is intended to allocate more references into registers when aliases do not appear in a region of code. When possible aliases are assumed by the compilers, speculative register promotion with hardware support is able to further improve register promotion. This paper addresses how to use the advanced loads address table (ALAT) in speculative register promotion. A compiler algorithm for speculative data flow analysis is proposed. Then the traditional partial redundancy elimination can be applied. The transformations based on the ALAT arediscussed. Experiments with SPEC CPU2000 are conducted to reveal the potential of speculative register promotion, the precision of our alias speculation, and the efficiency of ALAT. The results show that our algorithm is able to speculatively locate the candidates with high precision. The execution time on Itanium machines of one benchmark, equake, can be reduced 17% by the speculation register promotion. The tradeoffs in the hardware support for speculative register promotion are analyzed.