Wirelength-driven Analytical Placement for FPGA

Abstract

With increasing complexity of modern circuit, FPGA demands to be dealt with good CAD algorithm and suitable architecture to meet the lower non-recurring engineering cost and faster time-to-market. Placement is one of the crucial steps among them, as it decides time for implementing FPGA, routing resources and power consumption by digital circuits. Our research is centered on the placement algorithm for FPGA design. Simulated Annealing (SA) being the most popular among all the placement methods for quality results, takes huge compile time to implement larger circuits with the current new architectures. Researchers try to find a way for getting similar or better results with less run time. Based on the requirement, placement can be wirelength driven, timing driven and path driven. There are alternate ways of placement which are based on min-cut algorithm and analytic placement, and take less time. We targeted to optimize wirelength while doing placement using Gordian method in multiple iteration to get similar results as that of well-known academic research tool for FPGA - Versatile Place and route (VPR). Each iteration divides a subspace in four partitions and applies linear and bounding constraint to solve for quadratic optimization. We bypassed the placement methodology of VPR with our placement algorithm of analytical placement, implemented in MATLAB, and then fed back the output of our placer to the VPR flow for detailed placement and routing. We compare our results of placement and routing using 20 MCNC benchmarks and homogeneous VTR benchmarks with the VPR flow. Our MATLAB placer is faster by 38% with the expense of wirelength quality. It gets 1% better wirelength with 11% increase in runtime compared to the whole VPR placer after low temperature simulated annealing based final detailed placement.