Modeling and design space exploration of storage processing unit for energy efficiency

Abstract

Computer architectures in the present era of exascale computing and big data face two major challenges - (i) Increasing gap between processor and memory/storage speeds and (ii) Energy Consumption. A compute system that tightly couples data storage and computation is an attractive solution to mitigate these challenges. By implementing processing inside NAND Flash SSDs computation is moved closer to data. In fact, a computational hierarchy, named Storage Processing Unit (SPU), is formed with processing elements in NAND Flash Memory Controller, SSD controller and host general purpose processor. This hierarchy offers unique opportunities to curtail data movement and reduce energy consumption. This thesis models SPU architecture, explores the design space using carefully chosen applications and associated optimizations to understand and evaluate its energy and performance. Sparse BLAS, BFS, K-Means Clustering and K-Nearest Neighbor are used as benchmarks with energy and performance gains observed up to 11x-400x and 4x-66x respectively.