High Linearity Receiver In The Presence Of Blockers: Circuit Design And Layout Automation
2023-09
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High Linearity Receiver In The Presence Of Blockers: Circuit Design And Layout Automation
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2023-09
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With Internet-of-Things (IoT) devices and smartphones getting connected to the 5G network, the number of inter-connected devices has grown exponentially. This interconnectivity between devices will continue for future communication networks such as 6G and beyond. As the number of connected devices sharing the frequency spectrum increases, desired radio signals between two devices get jammed by the interference from other connected devices. If the jammer signal power increases up to a certain threshold, the desired radio signal is completely blocked, and it cannot be decoded at the receiver end. Thus, it is important to reject the jammer/blockers at the receiver end to receive and decode the desired signals. There are two types of blockers depending on the frequency band of interest: inband and out-of-band blockers. Typically, out-of-band blockers are rejected using a spectral filter in the receiver. Spectral filters such as band pass filter, SAW filter, etc. have been an integral part of the receiver design since the 2G standard, and therefore, out-of-band blockers are not a major concern for future communication systems. Since the in-band blockers are located inside the frequency band of interest, the spectral filter cannot reject these blockers. Hence, in-band blockers are a major concern for future communication systems and they need to be filtered out using a different filter.
This dissertation initially focuses on the design of spatially and spectrally passive MIMO receiver, which can reject both blocker types (in-band and out-of-band). The design involves use of spatial information from multiple antennas to create a spatial filter. This spatial filter can be used to filter out in-band blockers from the system. Additionally, the spatial filter and spectral filter in the MIMO receiver are created using passive techniques such as N-path mixers, resistors and capacitors, etc. This helps in improving the linearity of the MIMO receiver. Measured results of our 4-antenna MIMO receiver prototype achieved an in-band/in-beam B1dB of –10.6 dBm, which was 32 dB higher than other state-of-art designs. The performance of analog/RF circuits, such as the MIMO Receiver, depends on the careful layout design to reduce parasitics. Reducing parasitics, such as resistance and capacitance, leads to optimum design performance. Hence, there are many layout iterations to minimize the parasitic. This numerous iteration leads to a more extended design time for RF circuits.
Analog circuits, instead of digital logic circuits, have non-standard test benches for simulating and verifying the design. Since digital logic circuits had standard test benches to verify functionality, it led to the automation of digital logic synthesis and layout. On the other hand, a layout engineer manually crafted analog circuit layouts due to different layout requirements and non-standard test benches. Moreover, the layout rules become more restrictive as semiconductor technology scales from bulk CMOS to advanced node FinFETs. With other analog/RF circuits, the layouts differ in placement and routing rules leading to longer design time. Thus, the other part of this dissertation focuses on layout automation of analog/RF circuits using the open-source tool ALIGN. ALIGN identifies common analog design primitives inside the hierarchy of top-level circuits to create a DRC clean layouts of primitives. Once the primitive layouts are created, and the design hierarchy is identified, ALIGN completes the placement and routing of the design block from bottom-to-top levels of the hierarchy. The measured result of the MIMO receiver with an ALIGN-generated layout showed a performance similar to the manually crafted layout. Thus, analog layout generation can be automated to reduce design time and improve productivity without reducing performance.
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University of Minnesota Ph.D. dissertation. September 2023. Major: Electrical/Computer Engineering. Advisor: Ramesh Harjani. 1 computer file (PDF); xvii, 192 pages.
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Poojary, Jitesh. (2023). High Linearity Receiver In The Presence Of Blockers: Circuit Design And Layout Automation. Retrieved from the University Digital Conservancy, https://hdl.handle.net/11299/258881.
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