Electronic Design Automation for Layout Synthesis and Reliability Analysis of Analog and Mixed-Signal Circuits

Abstract

The market for analog and mixed-signal (AMS) circuits has grown significantly in recent years and is expected to show a similar trend in the foreseeable future. However, compared to their digital counterparts, AMS circuits have not seen adequate progress in developing design methodologies for automated circuit design and optimization or in developing techniques that can ensure reliable performance over their lifetime. These results in inefficiencies in the design cycle and could lead to significant failure rates in mixed-signal system-on-a-chip (SoC).Consequently, there is a strong need for comprehensively automating AMS circuits' physical design and developing techniques for analyzing and improving analog circuit reliability. In AMS physical design automation, two of the most significant challenges relate to parasitic optimization and symmetry detection. An analog/mixed-signal designer typically performs circuit optimization, involving intensive SPICE simulations, on a schematic netlist, and then sends the optimized netlist to layout. A vital constraint during layout generation is maintaining symmetry requirements that avoid performance degradation due to post-manufacturing mismatch between circuit elements. These constraints are usually user-specified or may be detected by invoking an external tool. In addition, the layout must avoid large interconnect parasitics on critical nets to achieve high performance. Today, identifying these performance-critical nets is a manual task that is laborious and potentially error-prone. Furthermore, the parasitics on these nets can be correlated: even if such critical nets are identified, the mere annotation may not be enough for high-performance AMS circuit design, and their correlations must be modeled during circuit optimization. The initial part of the thesis proposes two frameworks that boost the quality of the automated analog layout. The first framework automatically extracts the interdependence among the interconnect parasitics and builds machine learning (ML) models that can rapidly predict whether a placement configuration encountered during optimization meets performance specifications. The ML models are embedded into the cost function of a simulated-annealing-based placement engine to steer it towards layout configurations that optimize routing parasitics to meet the electrical constraints on the design. The approach is applied to build layouts for several analog blocks and shown to be effective. The second framework proposes a novel charge flow (CF) formulation that simultaneously addresses symmetry detection and parasitic optimization problems of AMS circuits. By leveraging schematic-level simulations, available "for free'' from the circuit optimization step, the approach alters the objective function to emphasize the reduction of parasitics on performance-critical nets and identifies symmetric elements/element groups. The effectiveness of the CF-based approach is demonstrated on various circuits within a stochastic placement engine. The latter part of the thesis focuses on analog reliability. Continuous downscaling of planar MOSFETs and the introduction of FinFETs have pushed aging-induced lifetime reliability issues to the forefront of both digital and analog design. Device degradation mechanisms such as bias temperature instability (BTI) and hot carrier injection (HCI) have acquired increased significance in FinFET-based designs, where elevated temperatures due to the self-heating effect (SHE) accelerate transistor aging due to BTI and HCI. Due to the matching requirements, AMS circuits are more sensitive to temporal aging degradation than digital circuits. In addition, fundamental differences in the working principle of AMS circuits, such as the need to apply a constant bias to fix an operating point of analog circuits and the application of diode-connected transistors, make AMS designs more susceptible to aging than digital circuits. This thesis presents two works that study the impact of aging-induced temporal degradation in two critical components of high-speed links, a delay-locked loop (DLL) and a feed-forward equalizer (FFE). The analyses illustrate how aging affects the building blocks of these two circuits and shows a pathway to analyze AMS design at various hierarchical levels.