Stress-Induced Performance Variations In 3D And Flexible Circuits

Abstract

Mechanical stress is a significant source of variability in advanced VLSI technologies that impacts circuit performance. Unintentional mechanical stress induced either by the manufacturing process or during daily use affects transistor electrical parameters such as mobility and threshold voltage due to piezoresistivity and stress-induced band deformation, respectively. Consequently, the performance of circuits/systems is highly dependent on stress distributions. Thus, the modeling of stress effect is important and necessary in the performance analysis of circuits and systems to meet design specifications. Mechanical stress is expressed in various ways in different integrated systems. In 3D ICs, which are implemented by stacking multiple ultra-thin chips (UTCs) in the vertical direction with through-silicon-vias (TSVs), thermomechanical stresses are induced due to the mismatches among various materials during the annealing process. For UTCs and organic thin-film transistors (OTFTs) that are widely adopted in the strongly emerging market for flexible electronics, such as flexible display and flexible system-in-foil (SiF), significant stress can be induced by deformations during normal operations. This thesis conducts stress-induced performance evaluations of three main application fields in 3D DRAMs, flexible displays, and flexible SiFs. The first part of the thesis addresses TSV-based 3D-stacked DRAMs, which can significantly increase cell density and bandwidth while also providing lower power consumption than their 2D counterparts. However, 3D IC structures experience significant thermomechanical stress due to the differential rates of contraction of their constituent materials, which have different coefficients of thermal expansion. This induces stress impacts on circuit performance. We develop a procedure that performs a performance analysis of 3D DRAMs, capturing the impact of both layout-aware stress and layout-independent stress on parameters such as latency, leakage power, refresh power, area, and bus delay. The approach first proposes a semianalytical stress analysis method for the entire 3D DRAM structure, capturing the stress induced by TSVs, micro bumps, package bumps, and warpage. Next, this stress is translated to variations in device mobility and threshold voltage, after which analytical models for latency, leakage power, and refresh power are derived. Finally, a complete analysis of performance variations is performed for various 3D DRAM layout configurations to assess the impact of layout-dependent stress. We explore the use of alternative flexible package substrate options to mitigate the performance impact of stress. Specifically, we explore the use of an alternative bendable package substrate made of polyimide to reduce warpage-induced stress and show that it reduces stress-induced variations, and improves the performance metrics for stacked 3D DRAMs. The second part of the thesis addresses stress effects in flexible displays with OTFTs, which are widely used in flexible circuits such as flexible displays, sensor arrays, and radio frequency identification cards (RFIDs). These technologies offer features such as better flexibility, lower cost, and easy manufacturability using a low-temperature fabrication process. Due to their very nature, flexible displays experience significant mechanical strain/stress in the field due to the deformation caused during daily use. These deformations can impact device and circuit performance, potentially causing a loss in functionality. In this part of work, the effects of extrinsic strain due to two fundamental deformations modes, bending and twisting, are first modeled. Next, this strain is translated to variations in device mobility, after which analytical models for error analysis in the flexible display are derived based on the rendered image values in each pixel of the display. To rectify strain-induced errors, two error correction approaches for flexible displays are then proposed, based on voltage compensation and flexible clocking. The third part of this thesis studies silicon-based UTCs that provide an excellent solution to build flexible SiFs for bio-sensing and bio-monitoring purposes. These UTCs use flexible chips that are thinned down to about 20$\mu$m, and utilize CMOS devices that deliver much higher performance than alternatives such as organic devices and thin-film transistors (TFTs), while being compatible with other SiF components such as flexible displays and flexible sensor arrays. Flexible SiFs experience significant mechanical stress in the field due to the deformation caused during normal use, which causes undesirable circuit performance shifts. We model the stress due to two types of packages schemes for UTCs with various chip dimensions, translating stress to shifts in device mobility and threshold voltage, and evaluate the system-level performance variations of two common SiF elements, an A/D converter and an SRAM.