A Study on Unintentional and Intentional Sources of Variability in Nanometer Scale Digital Circuits

Abstract

As technology has scaled aggressively over the past 50 years, device reliability issues and escalated power dissipation have become growing concerns in digital very large scale integrated (VLSI) circuits. Today's integrated circuits, which implement digital systems with billions of transistors in about a square centimeter, are tremendously susceptible to inadvertent errors, and circuit modifications required to ensure error resilience incur significant power overheads that are growing alarmingly as transistor dimensions shrink. Technology scaling has thus caused a resounding effect on the performance of digital circuits due to process, voltage, temperature, and usage-related variations, and increased power dissipation, resulting in lower battery life and increased system costs. Unintentional reliability failures due to circuit aging pose serious threat for safety-critical and security applications, and must be mitigated. Intentional errors, on the other hand, can be introduced to a limited extent in circuits pertaining to error-tolerant applications, to reduce the system power without significantly affecting user experience. In this thesis, we study these two aspects of circuit reliability, i.e., the unintentional reliability failures arising out of circuit aging, and the intentional unreliability introduced in circuits implementing error-tolerant applications to reduce system power. Temporal variations are injected into circuits due to aging during the normal operation of a chip. The predominant aging effects that cause circuit delay shifts over time are bias temperature instability (BTI) and hot carrier injection (HCI), both of which cause long-term degradations in transistor performance, and result in unintentional reliability issues in circuits. These effects are exacerbated as transistor sizes reduce, causing temporal delay degradations at the circuit level, thus introducing inadvertent errors during computations. Typically, these errors are mitigated by guardbanding through circuit overdesign or by increasing the supply voltage to speed up the systems. However, both result in wasted system power, and there is a need for effective aging estimation, so that just enough adaptive techniques can be applied, for error-free operation of a circuit. On the other hand, numerous applications related to recognition, mining, and synthesis, especially those from image and audio processing domains, are error tolerant, since they pertain to the inherently limited human perception. A new design paradigm called approximate computing, leverages this error-tolerance to implement arithmetic operations through approximate circuits. In other words, circuits implementing these applications can be intentionally designed to be unreliable, to achieve significant speed-up and system power savings through simplified hardware to perform complex arithmetic operations. The desired accuracy is often a user-specified input, and a there is a need to quantify the error injected into a computation as a function of the extent of approximation to systematically obtain the tradeoff between accuracy and power savings achieved in approximate circuits to aid their design. For applications where aging-related errors are a critical problem, the first half of the thesis proposes efficient aging sensor schemes that enable system adaptation for error-free operation. On-chip ring-oscillator-based (ROSC-based) structures are chosen as the surrogate aging sensors and this thesis presents a method for inferring circuit delay shifts due to BTI and HCI aging from these sensors. The proposed method efficiently computes calibration factors that translate delay shifts in the ROSCs to those in the monitored circuits within 1% of the true values. These factors are shown to be independent of temperature and supply voltage variations in practice. Further, a refinement strategy is proposed where the sensor measurements are amalgamated with infrequent online delay measurements on the monitored circuit to partially capture its true workloads, leading to 8% lower delay guardbanding overheads compared to the conventional methods. For error-tolerant applications, the second half of the thesis proposes algorithms for error analysis, and design of approximate circuits. The proposed analysis algorithms generate the distribution of the error injected into a computation when implemented using approximate arithmetic circuits. These algorithms are based on the Fourier and the Mellin transform to efficiently compute the total error accumulated at the output of an approximate circuit abstracted as a directed acyclic graph, through its topological traversal. The resulting error distribution is obtained much faster than Monte Carlo simulations, with the error statistics being within 2% of their true values. The proposed design algorithm uses the second moment of this distribution as a guideline to construct approximate arithmetic circuits through an optimization problem which maximizes their power savings while constrained by a user-specified error budget. Fast heuristics have been proposed to solve the integer non-linear optimization problem, and over 30% improvement in power savings is achieved compared to the conventional methods.