Design of Low Power Integrated Radios

Abstract

In this thesis, circuit techniques pertinent to low power CMOS integrated radio design compatible with IEEE 802.15.6 standard are presented. Low power radios are in increasing demand with the advent of an era of the Wireless Body Area Networks and Internet of Things. The performance of the proposed techniques has been verified by fabricating them in two standard CMOS processes: TSMC's 65nm and IBM's 130nm process. These designs are compatible with all the channels defined in IEEE 802.15.6 standard in the frequency range of 2.36 GHz to 2.484 GHz. First, an IEEE 802.15.6 compliant 2360-2484MHz multiband transmitter is presented that digitally multiplexes the appropriate phases from an 800MHz poly-phase filter output to generate π/4 DQPSK signals at 2.4GHz using injection locking. Modulation at 1/3rd the RF frequency reduces the transmitter power consumption and enables channel selection using an integer N PLL running at 800MHz. The modulation technique does not require phase calibration and resolves the problems of traditional injection lock based modulators. The prototype transmitter implemented in IBM's 130nm technology consumes 2.4mW while delivering -10dBm RF power at the TX output resulting in an energy efficiency of 2.5nJ/bit at 1.2Mbps raw data rate. The measured RMS EVM for π/4 DQPSK modulation is 3.21%. Next, a 2.3-2.5 GHz low-power low-noise 0.7 V mixer-first RF frontend for an IEEE 802.15.6 narrowband receiver is presented which uses frequency translated mutual noise cancellation based on passive coupling. Unlike traditional noise cancelling techniques we perform symmetrical noise cancellation of a fully differential structure where each path cancels the noise of the other at IF. This prototype design realized in TSMC's 65nm CMOS tackles the noise figure and power consumption problems of sub 1V mixers. The figure of merit (FOM) is 10 dB higher and the power consumption is 194 μW which is 0.5X lower than the state of the art. The local oscillator (LO) power used is only -14 dBm. Next, a 0.7V 2.3-2.5GHz ultra low power low noise amplifier (LNA) suitable for WBAN and Internet of Things (IoT) is presented which uses 1:3 balun at the frontend to achieve mutual noise and non-linearity cancellation as well as power reduction. In this technique the mutual coupling between the two secondary coils of the balun enable noise and non-linearity cancellation of both the main and the auxiliary path and therefore power consumption in the auxiliary path can be reduced. The step up balun reduces power by relaxing the transconductance (gm) requirement for matching of the input transistors. The circuit further exploits current reuse and gm boosting to reduce power consumption. This technique improves the noise figure by 2dB and IIP3 by 4dB while consuming 520μW of power. The FOM is 28.5dB which is 8dB better than the state of the art. The design is fully integrated with onchip balun and has been implemented in TSMC's 65nm technology. Finally, we present a fully integrated complete transmitter and receiver system with built in frequency synthesizer compatible with IEEE 802.15.6 standard (2.3-2.4 GHz) which has approximately 3X better energy efficiency than the state of the art in both transmit and receive. The synthesizer uses 7th harmonic injection locking to drastically reduce power. The transmitter uses an energy efficient fully programmable digital power amplifier with onchip matching network. The receiver has a zero IF I/Q architecture with zero power passive front end, energy efficient class AB baseband amplifiers with programmable gain/corner and a one bit comparator based ADC to substantially reduce power. The power consumption of the TX is 590μW, that of RX is 510μW and that of the synthesizer is 840μW. The design has been implemented in IBM's (now GF's) 130nm technology.