Secure, Resilient and Low-Energy Hardware Architectures for Internet-of-Things

Abstract

Modern devices are not only shrinking in size but also being increasingly connected to each other. These smart, connected devices are broadly termed Internet of Things or IoT. Examples of IoT applications range from safety critical automotive IoT employed in self-driving cars, smart cards and radio-frequency identication (RFIDs), high speed wireless sensor nodes, consumer electronics such as smart TVs, refrigerators and critical, life-saving systems such as implantables and medical devices. The devices used in these applications demand low cost, high efficiency and high security algorithms to be implemented using the most resource efficient platforms. To keep up with the changing application scenario, new architectural mappings and techniques for designs beyond traditional optimization has become a necessity. This thesis focuses on development of hardware architectures to achieve high endto- end security and low cost, low energy solutions using both Application-Specic Integrated Circuits (ASIC) designs and Field Programmable Gate Array (FPGA) implementations. The proposed architectures are targeted at ensuring security in manufacturing of semiconductor circuits, resilient communication between devices in safety critical systems, and low-energy solutions for machine learning applications. First, hardware obfuscation architectures for secure manufacturing are proposed. Hardware security has emerged as an important topic over the last decade due to reports of counterfeit devices detected in safety-critical defense systems. With the upcoming era of IoT, security is only going to increase in importance with more devices being manufactured and connected to a common network. Hardware obfuscation, which is dened as hiding functionality of designs and locking them using secret keys before sending for manufacturing, attempts to improve security of circuits. This technique ensures that the circuit is not understandable or usable by parties not possessing the correct secret key. Once the chips are received from the untrusted manufacturing units, they are unlocked and distributed to the end user, ensuring reliability. Development of novel architectures and schemes for obfuscation is the rst topic of my research. Second, Authenticated Encryption architectures for resilient communication are presented. Authenticated encryption with Associated Data (AEAD) is a form of encryption which simultaneously provides confidentiality, integrity, and authenticity assurances on the data. Authentication veries that the source of information is a trusted device and encryption ensures that the message has been protected from modications and eavesdropping across the channel. To ensure secure communication between two devices connected on the network, low cost and low power AEAD schemes are of paramount importance. To address design of authenticated encryption algorithms tailored towards changing application scenarios, a Competition for Authenticated Encryption: Security, Applicability, and Robustness (CAESAR) is currently in progress. Mapping of algorithms from CAESAR to low power and energy architectures using FPGA is my second topic of research. Finally, low energy machine learning architectures for biomedical internet-of-things are proposed. Biomedical applications such as implantable devices require low power and energy efficient architectures to perform machine learning tasks. For example, seizure detection aims to classify between resting and seizure state of electroencephalogram (EEG) signals. To differentiate between the two states, distinguishing features need to be extracted from these signals and classiers which are trained on large amounts of training data need to be employed. The units required to extract features involve power spectral density (PSD) computation and support vector machine (SVM) classi- ers, which require high energy. A technique termed approximate computing is applied to decrease the energy consumption of systems. Specically, applying bit-width reduction to modify architectures to lower energy consumption by incrementally increasing the precision in stages and using multi-level classiers while maintaining high sensitivity and specificity is the third focus of my research.