Browsing by Subject "electromigration"

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item
    Characterization of Integrated Circuit Reliability and Security Using On-Chip Monitoring Circuits
    (2018-07) Zhou, Chen
    This thesis has thoroughly summarized my six years of PhD research works in Electrical and Computer Engineering department, University of Minnesota. The novelty and contribution of my works is the evaluation of reliability and security on silicon chips using on-chip based approach. As has been fully explained in this thesis, on-chip based approach has several advantages: 1) high speed due to locally generated clock and data signals; 2) less test time from parallel operation; 3) low cost and flexible with fully custom controlled on-chip logic. Our EM works benefit a lot from the on-chip heater design. It has been proved to be very effective and robust for long time high temperature stress study. Temperature control requires dedicated power adjustment, which still has the room to be improved. Similar to previous published work, we found almost no failure effect under AC stress current. In order to study any potential weak effect of AC stress current, more test structure and approach are introduced in the 16nm FinFET tape-out. Unlike the low possibility in AC EM failure, failures on IC power grid have higher possibility and are more difficult to detect and characterize. The voltage tapping method adopted in our test chip has provided us great insight into the power grid EM failure. Our 16nm test chip includes more realistic power grid structure, which will help us to get better understanding in real chip EM failure. The hot carrier injection test work clearly indicated the saturation current variation shrinking phenomena resulting from self-heating induced temperature variation. Under DC stress condition, device with lower initial threshold voltage can conduct a higher current, associated with a higher temperature. Since HCI aging speed is positively related to temperature. Low threshold voltage devices end up with larger degradation, thus the saturation current variation is reduced. It is a good news for circuit design. However, the limitation of traditional DC stress mode need to be considered. To mimic the real chip operation, AC stress mode or pulsed current stress mode should be used instead of DC stress. Therefore, the self-heating induced temperature variation will be suppressed. Will we still see the same variation shrink phenomena under AC or pulsed current stress mode? This question may be answered in future work in this research community. Physical unclonable function is a promising silicon chip application due to the security requirement of Internet of Things (IoT) devices. PUF is a low cost solution for the security of IoT devices due to its compatibility of logic semiconductor process. Of the four metrics to evaluate the PUF design, uniqueness and randomness are usually easy to meet when symmetric layout is adopted. On the other hand, stability and security are much harder. The natural noise inside silicon devices and the condition variation can easily flip the responses which are weak biased originally. Modern modeling attach techniques are so powerful to compromise even the non-linear PUF systems. In my work, the on-chip sampling circuits help collect the real silicon data. A XOR based PUF system, together with the linear model based challenge selection scheme was proposed in my work to achieve both perfect stability and solid security. Although at the time when I graduate, the PUF circuits haven't been widely adopted by the industry, I hope its time will come in the future once the era of IoT devices arrives.
  • Thumbnail Image
    Item
    Electromigration-Induced Interconnect Aging and its Repercussions on the Performance of Nanometer-Scale VLSI Circuits
    (2016-06) Mishra, Vivek
    Modern electronic machines are powered by the integrated-circuit (IC), a semiconductor device consisting of compact electronic circuits on a silicon substrate. ICs can contain over a billion fundamental computing elements (transistors) that are connected by a network of metal wires called interconnects. Presently, interconnects constitute a primary bottleneck in achieving required IC performance. One of the major hurdles towards achieving good interconnect performance is electromigration (EM), a physical wear-out mechanism that occurs in metal wires carrying electrical current. EM is projected to limit the performance in future generations of ICs, especially for the wires carrying unidirectional (DC) currents, and is becoming a growing concern in on-chip interconnects across applications ranging from mobile computing to automotive domains. EM results in redistribution of metal atoms in interconnects that may result in the formation of either voids (empty spaces inside the wire) or extrusions (metal accumulation into the dielectric), and for modern copper-based interconnects, experimental works have observed that failure happens typically through the formation and growth of voids. For modern interconnects carrying large current densities, EM-induced voids can cause a resistance increase in the wire, rendering a wire EM-mortal. The resistance increase in these mortal interconnects can potentially result in circuit performance failure within the lifetime of a product. The classical methods for EM circuit analysis that are used in the industry to design EM-safe ICs do not capture the reality of EM physics in the realm of modern copper-based interconnects. IC designers use simple, deterministic, empirical EM models and there is a significant gap between such empirical models and the physics-based models that accurately capture the effect of EM in interconnects. The focus of this thesis is to attempt to reduce this gap by combining the two types of models efficiently, capturing the essence of physics-based models into the IC design, thereby enabling the design of EM-robust IC in future technologies. Unlike the classical EM analysis methods that rely on determining failure by extrapolating the EM characteristics of isolated single wires to IC operating conditions, the approach described in this thesis captures the circuit context and uses system failure rather than single-wire failure as the criterion for determining the lifetime of a circuit. The first part of the thesis proposes a statistical framework to evaluate the circuit performance degradation in on-chip wires through circuit level analysis. Typical on-chip power grids are inherently robust to EM due to redundancies in the interconnect network structure. In these grids, where interconnects typically carry unidirectional currents, the traditional approach to EM analysis is based on the weakest link model, whereby a single wire failure causes the grid to fail. It is shown here that the power grid can maintain supply integrity even under multiple elemental failures, and this can result in longer and more realistic lifetime predictions as compared with classical approaches. The next part of the thesis addresses signal interconnects that carry bidirectional (AC) currents as they transport logic signals within the digital system. For these wires, it is shown that EM is not only a catastrophic failure problem, but is also capable of causing parametric shifts in circuit performance over time. We perform HSPICE-based Monte Carlo simulations on a standard on-chip structure to quantify the impact of EM on circuit performance degradation. Although the damage due to EM degradation under bidirectional currents is reduced relative to the unidirectional current case due to partial EM recovery, it is demonstrated that, depending on the level of recovery, the circuit performance may degrade beyond acceptable limits and can be comparable to other transistor degradation mechanisms. The third part of the thesis addresses the issue of EM mortality in interconnects. A wire may be prevented from being mortal under EM if the maximum stress build-up, corresponding to the equilibrium between the current-induced forward stress and the back stress due to the gradient in atomic concentration along the wire, does not exceed the critical stress due to void nucleation. Alternatively, it may also not be mortal if the stress build-up does not exceed the critical stress over the lifetime of the circuit. A new efficient approach, based on multiple filters, is developed for determining the mortality of wires in a circuit. These filters greatly reduce circuit analysis time by predicting which wires can never be mortal over the circuit lifetime under its operating conditions so that detailed analysis must only be performed over a small subset of all interconnects. The final part of the thesis studies the effect of EM on via arrays, which redundantly connect the wires in multiple levels of metal in an IC. A stress analysis technique for via arrays is proposed, accounting for differential coefficients of thermal expansion in the materials that make up these structures. The combined impact of thermomechanical stress and redundancy on the via array is determined, and a new model for the impact on the failure of a larger interconnect network is developed. Using the new model, we analyze the EM-induced performance degradation in via arrays of an industrial power grid benchmark circuit.