Browsing by Subject "circuit reliability"

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    Characterization of Analog and Mixed-Signal Circuit Reliability Issues Using On-Chip Monitors
    (2020-01) Park, Gyusung
    As CMOS technology continues scaling down, reliability issues have become more challenging with each technology node. With this trend, the reliability on devices and digital gates have been well studied and characterized. However, despite the growing interest in analog/mixed-signal (AMS) circuit reliability, the reliability characterization in AMS circuits has not be widely reported due to complexity of the circuit and the difficulty in measuring subtle performance shifts. It is as such more sophisticated and difficult to characterize and understand as compared to the reliability of a simple transistor and a digital logic. Off-chip measurements for AMS reliability characterization can be considered using several off-chip components such as high-speed probes, off-chip drivers (OCDs), and a spectrum analyzer. But, it requires sophisticated interconnecting cables, packages, or connectors which needs expensive design effort. Also, each of these components can introduce inaccuracy in the measurement. This is critical for the aging testing of the noise sensitive AMS systems. To this end, we propose several on-chip in-situ monitoring circuits enable noise immune and high precision aging testing. In the first part of this thesis, we explore the impact of device aging on the frequency and phase noise degradation in an all-digital phase locked loop (ADPLL), which is a key building block for processor clock generation and wireless communication. This work presents frequency and phase noise degradation data measured from a standard ADPLL circuit fabricated in a 65nm process, using simple on-chip monitoring circuits. Our study shows that precise measurement of aging-induced timing shifts in ADPLLs is possible using digital circuits such as counters, flip-flops, and a programmable delay line. The proposed approach does not require an extensive test setup and allows automated testing using a simple serial interface. Experimental data shows that ADPLL phase noise degrades with aging even though the output frequency is maintained constant due to the ADPLL feedback operation. Results show that applying high temperature annealing can recover most of the phase noise degradation while natural recovery alone was not enough to fully recover the phase noise due to permanent hot carrier injection (HCI) and bias temperature instability (BTI) damage. In certain high-reliability applications where parts cannot be easily replaced and a long lifetime must be ensured (e.g. space electronics), annealing using an on-chip heat source may be a viable option. In addition to that, in this thesis, we experimentally explore reliability of an analog-to-digital converter (ADC). A counter based measurement circuit is proposed for in-situ ADC non-linearity measurements such as differential non-linearity (DNL) and integral non-linearity (INL). An array of counters collects the histogram of the ADC output codes for a triangular input voltage. Since the ADC operation and data transfer operation are separated in time, the DNL and INL results are immune to noise in the measurement setup. Using the proposed measurement method, we studied short-term BTI effects in a successive-approximate-register (SAR) ADC under different operating conditions. The test chip was fabricated in 65nm CMOS. Results confirm that subtle DNL shifts can be accurately measured using the proposed method. Next, an on-chip reliability odometer based on a ring oscillator array with dual power rails is proposed for the first time, which is capable of characterizing all four types of BTI modes at a single system. These four BTI stress can be occurred in either digital or analog building blocks in a system. Thus, it enables to fully characterize the degradation of all the digital and analog circuit components caused by four different BTI stress in the system. Stressed ring oscillators with independent dual power rails are implemented in which odd and even stages of an inverter chain are subject to different stress voltage configurations. An on-chip beat frequency detection circuit with 3 reference ring oscillators achieves a frequency measurement resolution as low as 0.01% with a short measurement interruption time of 1µs. Extensive BTI data collected from a 65nm ROSC array is presented for different stress conditions. Lastly, in this thesis, an Op-AMP reliability odometer using an on-chip monitor, on-chip signal generator, and an on-chip heater is proposed for the first time in 65nm CMOS process. A comparator and a counter are implemented to monitor the Op-AMP output before and after the stress. Two monitoring methods are employed: (i) monitoring output transient response for a square wave input, and (ii) monitoring output transient for power/load transition. The proposed on-chip heater enables the precise on-chip temperature control. Also, the on-chip monitor and signal generator achieve accurate aging dynamics characterization for the Op-AMP transient response. To sum up, several simple on-chip monitoring circuits are proposed to characterize circuit reliability aspects in the AMS systems such as ADPLL, SAR-ADC, and Op-AMP. Also, we propose the new BTI odometer for sensing all four BTI stress effects at a single system. Their performance are verified with the measurement results obtained from working test chips implemented in 65nm LP and GP CMOS technologies. Moreover, in-situ measurement schemes employed in these circuits enable accurate measurement without requiring sophisticated measurement setup for the noise sensitive AMS systems.