Browsing by Subject "Soft Error"

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    Circuit Techniques For Characterization Of Radiation-Induced Soft Errors In Advanced Cmos Processes
    (2018-05) Kumar, Saurabh
    Soft errors induced by particle strikes have been a major concern in reliability critical applications such as defense, space, medicine and finance etc. A number of radiation particles present in the ambient environment can induce errors in circuits which can result in system failure. These can be charged particles such as alpha, electrons, protons or heavy ions or neutral particles like neutrons, laser etc. Radioactive impurities like Uranium and Thorium in chip and packaging materials emit alpha particles that contribute towards errors. Protons, electrons and neutrons are found in space and terrestrial environment that can induce soft errors. When these particles penetrate the silicon, electron hole pairs are generated along the tracks that may be collected by the p-n junctions via drift and diffusion mechanisms. If the collected charge is large enough, the logic state of the junction may change, resulting in what we refer to as a soft error. Continuous process scaling has resulted in shrinking of device features that results in smaller junction area and lower strike probability at or around the junction that can lead to an error induction. The transistors, therefore, have become more and more resilient towards radiation-induced strikes. Advent of FinFET technology has further increased the resilience of devices towards soft errors by employing narrow three dimensional source-drain features that inherently make it difficult for the charge to get collected quickly. However, with process scaling, device density per die has gone up exponentially which means more transistors can be packed in the same die area. This has resulted in a probable rise in overall soft error rate (SER) due to increased number of susceptible nodes. Hence although per device SER has gone down, chip-level SER still remains a critical reliability issue that needs to be dealt with. In order to come up with efficient circuit designs that are immune towards soft errors, it is necessary to accurately and efficiently characterize SER in the given process. In this work, novel circuits have been proposed that capture important circuit parameters impacting SER. First of these is the Back-Sampling Chain (BSC) circuit that employs highly sensitive detection chains with more than 9x sensitivity as compared to conventional circuits. Higher sensitivity is critical in SER characterization since it facilitates higher strike induction resulting in collection of large data in limited beam time. BSC chain is capable of detecting Single Event Transients (SETs), Single Event Upsets (SEUs) and Multi-Bit-Upsets (MBUs), with scalable architecture that can be scaled to millions of stages without compromising on the measurement accuracy. BSC circuit can measure the SET pulse parameters (width and amplitude) while sweeping the sensitivity points that helps in re-construction of individual strike pulses. This, to our knowledge, is the first work to show individual pulse re-construction. Secondly, we show the detailed analysis of neutron-induced soft errors measured from the flip-flop arrays implemented in 14nm FinFET CMOS. Depending on the strike location and circuit topology, the MBU patterns may differ which has been characterized and a qualitative first order analysis has been presented. Seven unique MBU patterns extracted from measured data have been studied and analyzed to find layout dependencies on MBU. Results show strong correlation between the inter-node proximity and MBUs. With lower proximity, MBU induction probability as well as MBU size goes up and vice versa. The multi-cell-cluster (MCU) analysis shows higher SER cross-section for smaller MCU cluster size while the bigger clusters have lower contribution towards overall MBU SER. Thirdly, a 14nm test chip employing a novel NAND/NOR readout chain for characterizing SER in combinational logic gates is proposed. The proposed test structure uses high density standard logic gates as detection circuit for sensing SETs that are then forwarded to a skewed NAND-NOR readout chain which funnels all SET pulses while expanding the pulse width to ensure they reach the final triple modular redundant (TMR) counter. The proposed circuit is compact, has a scalable architecture based on a unit cell layout, and incurs minimal area overhead. Different gate configurations (device size, threshold voltage, fan-out and chain length) were implemented in the 14nm test-chip and irradiated under a neutron beam to collect a massive amount of statistical data. Radiation data captures, for the first time, the impact of various circuit parameters on combinational logic SER in 14nm tri-gate technology.
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    Design and Characterization Techniques for Reliable and Secure Integrated Circuits
    (2017-02) Tang, Qianying
    For the past decades of years, device feature size has continued to shrink for achieving better performance at faster speed, lower power and higher circuit density. However, going to a smaller feature sizes also brings in reliability issues such as greater process variations and more aggressive performance degradation. To address these issues, circuits are designed with certain guard-band to avoid probable failures. In order to determine an appropriate guard-band, it is imperative to develop accurate and efficient methods for characterizing and collecting these reliability metrics. This dissertation considers two important circuit reliability issues: Random Telegraph Noise (RTN) and Radiation induced Soft Error. For characterizing the realistic impact of RTN on logic circuit, we proposed two on chip monitors using a 65nm and a 32nm process respectively based on a Beat Frequency Detection (BFD) technique. The impact of RTN on logic and SRAM performance was analyzed based on the measured data. In the chapter 3, a compact 2 Transistor (2T) radiation sensor with tunable measurement sensitivity implemented in a 65nm LP bulk process is presented. The 2T sensor array exhibits a 117X higher sensitivity as compared to a 6T SRAM cell under an alpha particle radiation test. Meanwhile, with the electronic devices become increasingly ubiquitous and interconnected, demand for secure system design has also increased. In particular, hardware-oriented security has emerged as a new solution to provide another dimension of security in additional to the conventional software-oriented security. Many of the hardware security primitives seek to leverage the process variation, in contrast to suppress it for the sake of performance, to against post-silicon attacks. For example, hardware security building blocks such as true random number generators (TRNGs) and physical unclonable functions (PUFs) employ the CMOS devices inherent variation to extract entropy: the former one takes advantage of the time-variant random noise and latter one is based on the manufacturing induced random variation. In this dissertation, one TRNG and two lightweight PUFs are presented. The TRNG measures the frequency difference between two free-running ring oscillators to extract random frequency jitter. Benefitted from the differential structure, the proposed circuit fabricated in 65nm TRNG test chips passed all 15 NIST tests without the use of any feedback or tracking scheme in a supply voltage range from 0.8V to 1.2V. The final part of the dissertation presents two lightweight PUFs that are based on existing Dynamic Random-Access Memory (DRAM) and Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) blocks respectively.