Browsing by Subject "SRAM"
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Item Adaptive Cache Power Management Strategies(2016-06) Selvan, VinothPower management in SRAM based caches was increasingly popular for the fact that leakage power consumption of cache hierarchies is comparable to the power consumed by logic cores. There are a number of power management techniques proposed using circuit design and architectural techniques to reduce leakage power in SRAM based memories. Existing techniques closely monitor the behavior of sub-array building blocks in caches and dictates when to enter and exit sleep mode. This global sleep control policy is conservative and inefficient as it requires a closed loop architectural support to make low power decisions. In this work, we introduce aggressive power management schemes which has local decision logic that maintains parts of the sub-array in sleep mode even during active phases of operation thus saving leakage and idle power. We propose and implement three micro-architectural techniques named DRAM-like refresh, column based sleep and bitline segmentation in the 128kb SRAM sub-array building block to adopt additional power management schemes that are enabled per idle cycle basis. In active mode, each of these methods achieve leakage and dynamic power reduction by activating only a portion of the sub-array while during sleep mode, DRAM-like refresh trades off sub-threshold and dynamic refresh power to save idle data retention power. Our evaluations show that these methods on an average can achieve ~20\% more leakage savings during sleep and up to ~75\% more average power savings during active and idle operation. The implementation comes with an area overhead of ~4-5\% without any impact on the memory occupancy ratio. Later, we perform architectural evaluations to exploit memory access pattern and reconfigure the power management control circuitry to dynamically operate based on the demand of the application during active and idle states thus achieving additional power savings compared to static schemes. We also recommend combinations of these adaptive power management schemes for different levels of memory hierarchy after profiling the memory access pattern of various workloads.Item Exploring Energy, Accuracy and Cost Trade-offs in Cache Architectures for Approximate Computing(2015-06) Srinath, Vinayak BhargavA processor's power consumption can be most efficiently reduced by lowering the supply voltage. But with reduced voltage levels comes the major concern of failure of memory circuits. ASIC designers define a minimum operable voltage of the processor's on-chip cache often referred to as the Vccmin which is the voltage level below which the processor's memory-subsystem is no longer reliable. This guard-banding mechanism adds an additional overhead on the processor's memory-subsystem which does not allow it to operate below this voltage, and its important to note that the processor's memory-subsystem is one of the major contributors of its overall energy consumption. Guard-banding mechanisms are not just limited to increased minimum operable voltages and they result in large overheads. If certain restrictions are relaxed on the reliability of the output we can obtain significant savings in energy by eliminating these guard-banding mechanisms. This work explores different configurations of architectures suitable for low voltage operation of image and video applications by outlining the energy, accuracy, area and performance trade-offs.