Browsing by Subject "Radio Frequencies"

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    Digitally Controlled Phase Shifters and True Time Delays at Radio Frequencies
    (2024-04) Dehmeshki, Diba
    This study offers presents a comprehensive examination of digitally controlledphase shifters and true time delays, highlighting their critical roles in beamforming networks within communication systems, radar technology, satellite systems, and precision timing measurements, which are essential in particle physics. Precision timing measurements will be a key tool at the HL-LHC, used to suppress pile-up and search for long-lived particles. To control a reference clock with sub picosecond accuracy, we fabricated a digitally controlled phase shifter using the TSMC 65nm process. This phase shifter comprises a chain of 66 cells, each with a digitally controlled coplanar waveguide that provides either a short or long delay, allowing phase control of a reference clock to a precision of 200 fs with a dynamic range of 12 ps. In another project, we developed a digitally controlled phase delay with a step of 280 femtoseconds and a dynamic range of 230 picoseconds. This increase in delay range is achieved by using an LC circuit for coarse delay along with a series of coplanar waveguides for fine delay. The design details, simulations, and comparisons with laboratory measurements are discussed, demonstrating how this ASIC stabilizes a digital clock to a precision of less than one picosecond. We also introduce an integrated microwave true time delay (TTD) phase shifter with active amplitude control for wireless front ends. This phase control uses distributed digital manipulation of wave propagation in an artificial transmission line. A chip prototype developed using the TSMC 65nm process achieves a group delay resolution of 0.28 ps and a loss variation under 1 dB. Active tuning provides up to 15 dB of amplitude modulation and reverse isolation of 27 dB or better throughout the Ku-band. This structure supports broadband linear delay control across multiband phased arrays. In our final segment, we propose a novel approach to phase shifter design that moves away from traditional binary and uniform phase steps. This section compares uniform and binary step designs, showing that while uniform steps minimize phase error, they also lead to higher losses and require more space. By using non-binary and non-uniform delay blocks, our designs achieve a balance of low phase error without significant losses. Detailed simulation results challenge existing paradigms in phase shifter design and demonstrate potential for enhanced performance within specific frequency ranges, marking an advancement in the field.