Browsing by Subject "Physical design"

Now showing 1 - 4 of 4
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    Archival of Traffic Data: Phase II
    (1998-12) Shekhar, Shashi; Tan, Xinhong
    Traffic centers gather information from traffic sensors at regular intervals, but storing the data for future analysis becomes an issue. This report details work to improve the speed and effectiveness of traffic databases. In this project phase, researchers redesigned the data model based on the previous phase's data model and decreased the storage requirements by one-third. Researchers developed a web-based Graphical User Interface (GUI) for users to specify the query of interest; the outcome of the performance tuning gave users reasonable response time. The beneficiaries of this effective database would include the driving public, traffic engineers, and researchers, who are generally not familiar with the query language used in the database management system. This report summarizes the detailed reference, such as benchmark query, sample data, table schema, conversion code, and other information.
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    Automatic Detection of Driver Fatigue - Phase III
    (Minnesota Department of Transportation, 1999-06) Kaur, Sarbjit Sing; Eriksson, Martin; Papanikolopoulos, Nikolaos P.
    Traffic centers gather information from traffic sensors at regular intervals, but storing the data for future analysis becomes an issue. This report details work to improve the speed and effectiveness of traffic databases. In this project phase, researchers redesigned the data model based on the previous phase's data model and decreased the storage requirements by one-third. Researchers developed a web-based Graphical User Interface (GUI) for users to specify the query of interest; the outcome of the performance tuning gave users reasonable response time. The beneficiaries of this effective database would include the driving public, traffic engineers, and researchers, who are generally not familiar with the query language used in the database management system. This report summarizes the detailed reference, such as benchmark query, sample data, table schema, conversion code, and other information.
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    The Next Wave of EDA: Exploring Machine Learning and Open-source Philosophies for Physical Design
    (2022-11) Chhabria, Vidya
    The slowdown in Moore's law, coupled with the insatiable demand for compute from today's emerging applications, has created the need for hardware systems far beyond current capabilities. Electronic design automation (EDA) tools are now challenged to build chips that not only compensate for slow down in scaling (design-equivalent scaling) but also provide high performance for both ML and non-ML applications, which use a variety of new architectural techniques and operate under stringent performance constraints. However, conventional EDA tools and EDA research are plagued by several challenges. First, they involve computationally expensive analysis and optimizations which increase design time-to-market. Second, they are heuristic-based and often tradeoff speed for accuracy which results in suboptimal solutions. Third, the closed culture within the community, expensive EDA tools, and complexity of EDA tools that demands expert users have created a high barrier to entry slowing down research. This thesis explores machine learning (ML) and open-source philosophies to address these challenges in EDA tools for physical design. Every stage of physical design involves the use of optimization algorithms, which invoke computationally expensive analysis, to minimize power and area and maximize the performance of the circuit. Three critical analyses that are performed several times during physical design are power delivery network (PDN) analysis, thermal analysis, and timing analysis. Optimization algorithms require these analyses to be fast and accurate to generate solutions that can drive design-equivalent scaling. While these analyses and optimization problems have been explored since the early 1980s, the advent of ML brings in novel solutions and an open culture that creates a new wave in EDA. The first part of this thesis shows how ML transcends conventional EDA tool challenges for power-related problems by (i) enabling vast speedups for PDN and thermal analysis with fast inference with high accuracy,(ii) providing optimized correct-by-construction PDN solutions, and (iii) aiding in PDN benchmark and dataset generation. To speed up conventional PDN and thermal analysis, this thesis maps them into image-to-image and sequence-to-sequence translation tasks, which allows leveraging a class of ML models with an encoder-decoder-based generative (EDGe) architecture. Once trained, these ML models are transferable across designs synthesized within the same technology and packing solution. The networks perform millisecond analyses with negligibly small errors against commercial tools that require several hours. Further, these EDGe networks are leveraged to develop MAVIREC, which can rapidly sample a large set of input vectors and provide recommendations for voltage drop analysis. While analysis diagnoses problems, it must be coupled with optimization techniques to solve these problems. The thesis proposes OpeNPDN, an ML-based methodology for PDN optimization that employs a set of predefined templates that serve as potential building blocks for the PDN. The optimization algorithm involves building a PDN that meets voltage drop and electromigration constraints while minimizing the wiring resources used. A convolutional neural network (CNN) is trained to select an appropriate PDN template for each region on the chip based on power, bump, macro, and congestion distributions. The CNN-based optimization rapidly frees thousands of routing tracks in congestion-critical regions, while staying within the voltage drop and electromigration (EM) current density limits. Although ML has found success in the problems described above, a major challenge has been the unavailability of benchmarks for evaluating these solutions. The thesis develops BeGAN, an ML-based methodology for synthesizing synthetic PDN benchmarks that obfuscate intellectual property information. The approach applies generative adversarial networks (GANs) and transfer learning techniques to create realistic PDN benchmarks from a small set of real circuit data. BeGAN generates thousands of PDN benchmarks released in the public domain in four open-source technologies. The second part of the thesis develops ML-based solutions for timing analysis and optimization. A critical part of timing closure is accurate crosstalk-aware timing analysis. However, existing crosstalk-aware static timing analysis (STA) techniques are limited due to their imprecise use of heuristics. The thesis proposes XT-PRAGGMA, a tool that uses GPU-accelerated dynamic gate-level simulations and ML to eliminate inaccuracies in crosstalk-aware STA tools and accurately predict crosstalk-induced delays. The proposed technique is fast and reduces falsely-reported total negative slack by 70% compared to traditional STA-based techniques. In addition to accurate analysis techniques, timing optimization algorithms are critical to successful timing closure. Logic gate sizing is one such NP-hard-constrained optimization problem that aims to minimize the circuit implementation cost (typically, area or power), subject to timing constraints. This thesis presents RL-LR-Sizer, a tool that applies Lagrangian relaxation techniques to a novel reinforcement learning (RL) framework to perform autonomous gate sizing. The RL framework trains a relational graph convolutional network agent to perform timing optimization. RL-LR-Sizer outperforms conventional algorithms and moves the Pareto optimal front of the area-delay tradeoff curve to the left on designs in a 45nm technology. The last part of the thesis aims to address challenges related to high barriers to entry and the closed culture in the EDA community, which hinder reproducible research and the adoption of ML-based techniques. It contributes to the open ecosystem by developing novel open-source EDA tools. The first is TherMOS, an open-source thermal model to estimate self heating effects in advanced transistors. Modern transistors such as FinFETs and gate-all-around FETs suffer from excessive heat confinement due to their small size and three-dimensional geometries. This results in device self-heating, which can reduce speed, increase leakage, and accelerate aging. The thesis uses TherMOS to characterize the temperature for both the 7nm FinFET and 5nm GAAFET sub-structures and analyzes the impact of temperature on circuit performance and reliability. The second is RTA-simulator, an open-source pattern-dependent transient rapid thermal annealing (RTA) simulator for analyzing RTA-induced variations due to differences in die layout patterns. Unlike prior art, RTA-simulator considers the temperature-dependent thermal conductivity of silicon. The thesis leverages RTA-simulator to analyze RTA effects on a 16KB SRAM and suggest strategies for RTA-induced variation mitigation for a 7nm FinFET SRAM design. The third is PDNSim, an open-source PDN analysis tool integrated with OpenROAD, for estimating voltage drop and EM current densities. With scaling, power densities and wire parasitics are on an increasing trend making PDN analysis an integral part of physical design. For the OpenROAD project, PDNSim serves two purposes. First, it performs static voltage drop estimation and current density estimation at various stages of the physical design flow after placement. Second, it checks the connectivity of the power grid to ensure that every standard cell receives power (voltage) from the pin (bump) and that all power stripes are connected. The thesis demonstrates the results of PDNSim on several designs in both open-source and closed-source technologies, which are being run as a part of the OpenROAD project regression tests.
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    Overcoming Physical Design challenges in nanometer-scale integrated circuits
    (2013-02) Wei, Yaoguang
    Through aggressive technology scaling over the past five decades, integrated circuit design has entered the nanometer-scale era. While scaling enables the design of more powerful chips, circuit designers must face numerous challenges that accompany these miniscule feature sizes. Many of these issues are expressed in the step of physical design, an important back-end stage in the integrated circuit design flow. First, the routability of a design becomes an increasingly important and difficult problem, and must be addressed across the entire physical synthesis tool stack. This in turn requires effective routability evaluation methods to be used in the early stages for congestion mitigation. Second, wire delays do not scale down well with process technology, and have exceeded the gate delay in importance, becoming the dominating factor that determines the circuit delay. Wire delays can be reduced by inserting large numbers of buffers, but these can significantly increase the chip area, cost, and power, so that improved methods that control these costs are essential. Third, with shrinking feature sizes, the impact of process variations has become more serious than before. Several important process variation effects show strong dependencies on the underlying patterns on the die, and these challenges can be addressed effectively through appropriate physical design. This thesis presents solutions to these challenges. To achieve effective routability evaluation, we first analyze the problems associated with mainstream global-routing-based congestion analysis tools. Two major deficiencies of existing approaches are: (i) they do not adequately model local routing resources, which can cause incorrect routability predictions that are only detected late, during detailed routing, (ii) the metrics used to represent congestion may yield numbers that do not provide sufficient intuition to the designer; moreover, they may often fail to predict the routability accurately. We propose solutions for both problems. First, we develop an efficient, accurate and scalable local routing resource model. Experiments demonstrate that our model improves the accuracy of a congestion analyzer and enables designers to use a coarser grid to speed up congestion analysis and achieve similar accuracy as the baseline case. Second, we develop a new metric that represents the congestion map for the chip with high fidelity. Experiments show that compared with conventional metrics, the new metric can predict the routability more accurately and can drive a placer to obtain a design that has better routability characteristics. To reduce the buffer usage, we make full use of the timing benefits brought by the thick metal layers. In advanced technologies, a larger number of metal layers with thick cross-sections are available for routing. These metal layers have much smaller wire delays than thinner layers, and assigning nets to these layers can improve timing and save buffer usage. However, existing algorithms have various limitations in using thick metal layers. In this work, we propose a novel algorithm to address the issue. Our algorithm tries to assign as many nets as possible to thick metal layers to maximize the timing benefits while simultaneously using heuristics to control the congestion at a manageable level. We also present a new physical synthesis flow that adds our algorithm as a new component at an early stage of an existing industrial design flow. Experimental results demonstrate the effectiveness of our algorithm and flow on a set of industrial designs. To overcome the challenges from process variations, this thesis presents physical design solutions to two important types of variations induced in the processes of oxide chemical mechanical polishing (CMP) and rapid thermal annealing (RTA). First, since the oxide CMP variation highly depends on the metal pattern density, a common practice to reduce CMP variation is to insert dummy fills. However, dummy fills have side effects on design performance or complexity and should be minimized. Therefore, we propose a novel global routing algorithm directly aiming to minimize the amount of dummy fills necessary to satisfy the requirements for CMP. Since it is not computationally efficient to directly minimize the amount of dummy fills in the routing process, we develop a surrogate optimization objective through theoretical analyses and experiments. Then effective cost functions are elaborated and applied in the routing process to optimize the surrogate metric. Our strategy and algorithm is validated by the experiments on a standard set of benchmark circuits. Second, since RTA variation strongly depends on the density of the STI regions, to minimize RTA variation, this thesis proposes a two-step approach to maximize the uniformity of the STI density throughout the layout. We introduce a concept of effective STI density and propose an efficient incremental method to compute it for the whole circuit. Furthermore, we enhance a conventional floorplanner to handle the new objective of minimizing the variations in effective STI density, using a two-stage simulated annealing heuristic. As the second step of our efforts, we insert dummy polysilicon fills to further minimize the variation in effective STI density. Experimental results demonstrate that our methods can significantly reduce the RTA variations.