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Browsing by Subject "Phase Locked Loop"

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    Single chip high-speed serial link communications for multi-channel and multi-standard applications
    (2008-11) Hsieh, Ming-ta
    This thesis presents new design concepts for high-speed serial link systems, including those for standards such as Serial AT Attachment (SATA), Serial Attached SCSI (SAS), Peripheral Component Interconnect Express (PCIe) and Fibre Channel (FC). The research work also provides for co-existing operation of multi-standards in a single chip for multi-channel, serial link communications systems. A high-speed serial link starts with low-frequency parallel data sampled by a synthesized clock and serialized into a stream of data. The serialized data is then pre-emphasized and transmitted to the receiver through a bandwidth-limited channel. The receiver equalizes the received signal in order to compensate the high frequency spectrum loss before extracting the clock and data in the Clock and Data Recovery (CDR) loop. Next, the extracted data is sampled by the recovered clock and deserialized back into a parallel set of signals. The complete system for serializing / deserializing data transmission from transmitter (Tx) to receiver (Rx) is known as a SerDes. This research starts with a system-level performance assessment, using a top-down behavioral- to transistor-level design approach and a bottom-up transistor- to behavioral-level verification procedure. Clock synthesizer design is studied and a new approach for a spread spectrum clock generator is proposed. Then, the design of a system with multi-level, bi-directional signaling is investigated. Finally, the study of high-speed CDRs for a variety of applications is presented. The design consists of 4 SerDes subsystems with three clock synthesizers, using two ring VCO based PLLs and one LC VCO based PLL. This design demonstrates the simultaneous operation of a multi-rate, multi-standard, multi-channel serial communication system in a single chip.