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Browsing by Subject "Parallelism"

Now showing 1 - 3 of 3
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    Computer Go and Monte Carlo Tree Search: Opening Book and Parallel Solutions
    (2016-05) Steinmetz, Erik
    This work examines two aspects of Monte Carlo Tree Search (MCTS), a recent invention in the field of artificial intelligence. We propose a method to guide a Monte Carlo Tree Search in the initial moves of the game of Go. Our method matches the current state of a Go board against clusters of board configurations that are derived from a large number of games played by experts. The main advantage of this method is that it does not require an exact match of the current board, and hence is effective for a longer sequence of moves compared to traditional opening books. We apply this method to two different open-source Go-playing programs. Our experiments show that this method, through its filtering or biasing the choice of a next move to a small subset of possible moves, improves play effectively in the initial moves of a game. We also conduct a study of the effectiveness of various kinds of parallelization of MCTS, and add our own parallel MCTS variant. This variant introduces the notion of using multiple algorithms in the root version of parallelization. The study is conducted across two different domains: Go and Hex. Our study uses a consistent measure of performance gains in terms of winning rates against a fixed opponent and uses enough trials to provide statistically significant results.
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    Exploring efficient architecture design for thread-level speculation---Power and performance perspectives.
    (2009-06) Packirisamy, Venkatesan
    With the advent of multi-threaded (e.g. simultaneous multi-threading (SMT) ) and/or multi-core (e.g. chip multiprocessors (CMP) [3, 4]) architectures, now the challenge is to utilize these architectures to improve performance of general-purpose applications. However, traditional parallelizing compilers often fail to effectively parallelize general-purpose applications which typically have complex control flow and excessive pointer usage. Thread-Level Speculation (TLS) have been proposed to simplify the task of parallelization by using speculative threads. Though the performance of TLS has been studied in the past, its power consumption, power efficiency and thermal behavior are not well understood. Also previous work on TLS have concentrated on multi-core based architectures and relatively little has been done on supporting TLS on multi-threaded architectures. With increasing multi-threaded/multi-core design choices, it is important to understand the benefits of the different types of architectures. The goal of this dissertation is to explore architecture techniques to efficiently implement TLS in future multi-threaded/multi-core processors. The dissertation proposes a novel cache-based architecture to support TLS in multi-threaded SMT architecture. A detailed study on the efficiency of different TLS architectures was conducted by comparing their performance, power and thermal characteristics. To improve efficiency, the dissertation proposes a novel SMT-CMP based heterogeneous architecture which combines the advantages of both SMT and CMP architectures. The dissertation also proposes novel architecture and compiler techniques to efficiently extract speculative parallelism from multiple loop levels.
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    Power management in multicore processors through clustered DVFS.
    (2010-07) Kolpe, Tejaswini
    The need for high speed processors in recent years has increased the need to exploit more parallelism than instruction level parallelism (ILP) and thread level parallelism (TLP). As a result, chip multiprocessors have emerged as a solution for the high speed computing demands. Though a high throughput is achieved, power dissipation in chip multiprocessors is still a problem that needs to be addressed. A number of techniques for reducing both the active and static components of power exist. Dynamic voltage and frequency scaling (DVFS) is one of the schemes to reduce active power. DVFS is easy to implement for a single processor but if it has to be implemented for each core of a chip multiprocessor, a number of voltage regulators are required on chip and the area and power overheads associated with them surpass the advantages of having per-core control. On the other hand, one DVFS control for all cores cannot fully harness the potential for power reduction in each core. In this thesis, we look at the possibility of clustering the cores of a multicore processor and implementing DVFS on a per-cluster basis. We propose a scheme to find similarity among the cores and cluster the cores based on the similarity. We also provide an algorithm to implement DVFS for the clusters. We evaluate the effectiveness of per-cluster DVFS in power reduction by considering different number of clusters and different use cases for the applications running on the cores.